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	<id>https://pct.wiki.uib.no/api.php?action=feedcontributions&amp;feedformat=atom&amp;user=Xej010</id>
	<title>pCT - User contributions [en]</title>
	<link rel="self" type="application/atom+xml" href="https://pct.wiki.uib.no/api.php?action=feedcontributions&amp;feedformat=atom&amp;user=Xej010"/>
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	<updated>2026-05-05T17:26:09Z</updated>
	<subtitle>User contributions</subtitle>
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	<entry>
		<id>https://pct.wiki.uib.no/index.php?title=%C3%85rhus_Testbeam_2023_Documentation&amp;diff=999</id>
		<title>Århus Testbeam 2023 Documentation</title>
		<link rel="alternate" type="text/html" href="https://pct.wiki.uib.no/index.php?title=%C3%85rhus_Testbeam_2023_Documentation&amp;diff=999"/>
		<updated>2023-08-23T12:38:33Z</updated>

		<summary type="html">&lt;p&gt;Xej010: Created page with &amp;quot;= DAQ = == Power Cycle == &amp;#039;&amp;#039;&amp;#039;Turn on the VCU118&amp;#039;&amp;#039;&amp;#039;  &amp;#039;&amp;#039;&amp;#039;Check if these two connections are available&amp;#039;&amp;#039;&amp;#039;  &amp;#039;&amp;#039;&amp;#039;Test pDTP&amp;#039;&amp;#039;&amp;#039;  &amp;#039;&amp;#039;&amp;#039;Turn on the Power Supply Unit&amp;#039;&amp;#039;&amp;#039; for ALPIDEs - Pres...&amp;quot;&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;= DAQ =&lt;br /&gt;
== Power Cycle ==&lt;br /&gt;
&#039;&#039;&#039;Turn on the VCU118&#039;&#039;&#039;&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Check if these two connections are available&#039;&#039;&#039;&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Test pDTP&#039;&#039;&#039;&lt;br /&gt;
&lt;br /&gt;
&#039;&#039;&#039;Turn on the Power Supply Unit&#039;&#039;&#039; for ALPIDEs - Press the ALL ON button&lt;br /&gt;
&#039;&#039;&#039;NOTE!&#039;&#039;&#039; that analog and digital need to be turned on/off at the same time, or analog first when powering on and digital first when powering off. Best practice to use ALL ON/OFF buttons.&lt;/div&gt;</summary>
		<author><name>Xej010</name></author>
	</entry>
	<entry>
		<id>https://pct.wiki.uib.no/index.php?title=Hardware_Documentation_and_Howto%27s&amp;diff=998</id>
		<title>Hardware Documentation and Howto&#039;s</title>
		<link rel="alternate" type="text/html" href="https://pct.wiki.uib.no/index.php?title=Hardware_Documentation_and_Howto%27s&amp;diff=998"/>
		<updated>2023-08-23T11:43:05Z</updated>

		<summary type="html">&lt;p&gt;Xej010: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;[[Main Page]] -&amp;gt; [[Hardware Documentation and Howto&#039;s]]&lt;br /&gt;
&lt;br /&gt;
== Getting Started ==&lt;br /&gt;
&lt;br /&gt;
* [[Getting Started VCU118|VCU118]]&lt;br /&gt;
* [[Getting Started PTB|PTB]]&lt;br /&gt;
&lt;br /&gt;
== Documentation ==&lt;br /&gt;
&lt;br /&gt;
=== pRU ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Clock_network.png | pRU Clock Network]]&lt;br /&gt;
* [[:Media:PRU Address Map.pdf | pRU Address Map]]&lt;br /&gt;
* [[:Media:PRU Ethernet Configurations.pdf | DCS and Data Offload Ethernet Configurations]]&lt;br /&gt;
* [[:Media:PDTP.pdf | pCT Data Transfer Protocol]]&lt;br /&gt;
* [[:Media:Data format v0.2.pdf | pRU Data Format]]&lt;br /&gt;
* [[:Media:FpgaCalc.ods | FPGA and ALPIDE radiation calculations]]&lt;br /&gt;
* [[:Media:Control Interface.pdf | pRU Control Interface]] [Deprecated, only in use on PTB. Replaced with IPBus on VCU118 + all other boards in the future.]&lt;br /&gt;
&lt;br /&gt;
==== pRU Registers and Bus System ====&lt;br /&gt;
[[File:Top level firmware.png|500px]][[File:Bus tree.png|500px]]&lt;br /&gt;
&lt;br /&gt;
The pRU bus system is connecting the various modules on the FPGA to a common master, the Microblaze Subsystem.&lt;br /&gt;
Each of the modules is associated with a given BASE-ADDRESS specified in the [[:Media:Control Interface.pdf | pRU Control Interface Document]].&lt;br /&gt;
Note that several instances do exist for certain modules. E.g. there are one alpide_data instance for each ALPIDE chip connected to the pRU.&lt;br /&gt;
To communicate with a specific instance one needs to add an offset of 0x1000 times the instance number to the module base address.&lt;br /&gt;
&lt;br /&gt;
E.g. if you want to communicate with the &lt;br /&gt;
&lt;br /&gt;
* 1st instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt;&lt;br /&gt;
&lt;br /&gt;
* 2nd instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt; + (0x1000 * (2-1))&lt;br /&gt;
&lt;br /&gt;
* 16th instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt; + (0x1000 * (16-1))&lt;br /&gt;
&lt;br /&gt;
===== Module Registers =====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Global_regs.pdf | global_regs]]&lt;br /&gt;
* [[:Media:Trigger_manager.pdf | trigger_manager]]&lt;br /&gt;
* [[:Media:Offload.pdf | offload]]&lt;br /&gt;
* [[:Media:Alpide_control.pdf | alpide_control]]&lt;br /&gt;
* [[:Media:Alpide_data.pdf | alpide_data]]&lt;br /&gt;
&lt;br /&gt;
==== PTB-specific Module Registers ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Power_control.pdf | power_control]]&lt;br /&gt;
* [[:Media:Ptb_regs.pdf | ptb_regs]]&lt;br /&gt;
&lt;br /&gt;
=== Transition Card (TC) ===&lt;br /&gt;
&lt;br /&gt;
*  [[Media:TC-v1.0_schematic.pdf | TC-v1.0 Schematic]]&lt;br /&gt;
&lt;br /&gt;
=== ALPIDE Chip ===&lt;br /&gt;
&lt;br /&gt;
* [[Media:Alpide manual ver3.pdf | ALPIDE Manual v0.3]]&lt;br /&gt;
&lt;br /&gt;
=== ALPIDE Bonding and Mounting ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Report_Feb_2019.pdf | 9-chip String Simulation - and proposed 9-chip string redesign - 2019 Feb ]]&lt;br /&gt;
&lt;br /&gt;
==== Chip Cable ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:2020_01_08.zip | 2020 January 8 ]]&lt;br /&gt;
* [[:Media:2019_05_16.zip | 2019 May 16 (ULTM)]]&lt;br /&gt;
&lt;br /&gt;
==== 9 Chip String ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:2019_11_05.zip | 2019 November 5 ]]&lt;br /&gt;
* Some of the aluminium traces on the flex cable broke by the tail of the cable (near the ZIF stiffener). [[Media:Tail_modifications.png | Current design and possible modifications]] shows the current design and two possible modifications. It has been decided that new designs will use the &#039;&#039;&#039;design 1 modification&#039;&#039;&#039; and &#039;&#039;&#039;longer ZIF-stiffener&#039;&#039;&#039; (30 mm long).&lt;br /&gt;
&lt;br /&gt;
=== Production Test Box (PTB) ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:PTB-v1.0_schematic.pdf | PTB-v1.0 Schematic]]&lt;br /&gt;
* [[:Media:PTB-v1.0_samtec.zip | PTB-v1.0 FPGA Connections]]&lt;br /&gt;
* [[:Media:PTB-v1.0_yamaichi.zip | PTB-v1.0 Yamaichi Connections]]&lt;br /&gt;
&lt;br /&gt;
=== FPGA Mezzanine Card (FMC) ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:FMC-v1.0_schematic.pdf | FMC-v1.0 Schematic]]&lt;br /&gt;
&lt;br /&gt;
=== mTower ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:mTower_schematic.pdf | mTower Schematic]]&lt;/div&gt;</summary>
		<author><name>Xej010</name></author>
	</entry>
	<entry>
		<id>https://pct.wiki.uib.no/index.php?title=Cooling_Documentation&amp;diff=997</id>
		<title>Cooling Documentation</title>
		<link rel="alternate" type="text/html" href="https://pct.wiki.uib.no/index.php?title=Cooling_Documentation&amp;diff=997"/>
		<updated>2023-08-23T11:41:47Z</updated>

		<summary type="html">&lt;p&gt;Xej010: Created page with &amp;quot;=== Cooling Final Design === === Cooling Simulations === === Cooling Measurements ===  === Cooling Laboratory Setup ===  1x LAUDA Ultracool UC 4 is used for water cooling in t...&amp;quot;&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;=== Cooling Final Design ===&lt;br /&gt;
=== Cooling Simulations ===&lt;br /&gt;
=== Cooling Measurements ===&lt;br /&gt;
&lt;br /&gt;
=== Cooling Laboratory Setup ===&lt;br /&gt;
&lt;br /&gt;
1x LAUDA Ultracool UC 4 is used for water cooling in the laboratory now ([https://www.lauda.de/pim/datasheet/LAUDA_UC4_E6004411_en_20211220_135424.pdf data sheet] and [https://cdn.accentuate.io/6800432890013/1624628180288/DMI-0210-01_UC_2-4__EN_.pdf?v=0 manual]).&lt;br /&gt;
&lt;br /&gt;
1x Digital flow switch with temperature sensor for the cold plate (flow rate 13,6 l/min) SMC PF3W520S-04-2T-R-X128 &lt;br /&gt;
&lt;br /&gt;
1x Digital flow switch with temperature sensor for the tracking layers (flow rate 3,2 l/min) SMC PF3W504S-03-2T-R-X128 &lt;br /&gt;
&lt;br /&gt;
2x Digital flow monitor (SMC PFG310-SV)&lt;br /&gt;
&lt;br /&gt;
4x Meas Heavy Industrial Pressure Transmitter (M5131-70010X-004BC)&lt;br /&gt;
&lt;br /&gt;
3x Axial fans 4-wire 12V&lt;br /&gt;
&lt;br /&gt;
1x I/O Module Moxa ioLogik E1212 (8x digital inputs, 8x digital inputs/outputs)&lt;br /&gt;
&lt;br /&gt;
1x I/O Module Moxa ioLogik E1240 (8x analog inputs)&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Moxa-iologik-e1200-series-manual-v15.10.pdf | Moxa E1200 Series manual]]&lt;br /&gt;
* [[:Media:Moxa-iologik-e1200-series-datasheet-v2.3.pdf | Moxa E1200 Series datasheet]]&lt;br /&gt;
* [[:Media:PCT_lab_setup.pdf | Schematic of the pCT lab setup]]&lt;/div&gt;</summary>
		<author><name>Xej010</name></author>
	</entry>
	<entry>
		<id>https://pct.wiki.uib.no/index.php?title=Main_Page&amp;diff=996</id>
		<title>Main Page</title>
		<link rel="alternate" type="text/html" href="https://pct.wiki.uib.no/index.php?title=Main_Page&amp;diff=996"/>
		<updated>2023-08-23T11:39:21Z</updated>

		<summary type="html">&lt;p&gt;Xej010: Documentation and Howto&amp;#039;s cleanup&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;&#039;&#039;&#039;Wiki for the proton CT project&#039;&#039;&#039;&lt;br /&gt;
&lt;br /&gt;
== Documentation and Howto&#039;s ==&lt;br /&gt;
=== Software ===&lt;br /&gt;
* [[Documentation|Software Documentation]] on how to install and use the involved software packages, how to use the GitLab service, and about the development workflow, etc.&lt;br /&gt;
&lt;br /&gt;
=== Hardware ===&lt;br /&gt;
* [[Hardware Documentation and Howto&#039;s]] on pReadout, ALPIDE bonding, Production Test Box, Transition Card&lt;br /&gt;
&lt;br /&gt;
=== Control &amp;amp; Readout Software ===&lt;br /&gt;
* [[Control &amp;amp; Readout Software Documentation and Howto&#039;s]]&lt;br /&gt;
&lt;br /&gt;
=== ALPIDE ===&lt;br /&gt;
* [[ALPIDE Documentation and Papers]]&lt;br /&gt;
&lt;br /&gt;
=== Cooling ===&lt;br /&gt;
[[Cooling Documentation]] on the cooling simulations, measurements, laboratory setup and the final design. &lt;br /&gt;
&lt;br /&gt;
=== Århus Testbeam 2023 ===&lt;br /&gt;
[[Århus Testbeam 2023 Documentation]] on the testbeam at Århus hospital including simulation, setup, equipment used, etc. &lt;br /&gt;
&lt;br /&gt;
== [[Publications]] ==&lt;br /&gt;
List of publications from the project.&lt;br /&gt;
&lt;br /&gt;
==== Workpackage Reports ====&lt;br /&gt;
* [[Media:pCT-WP1-1-Rev2 design recommendations.pdf | pCT-WP1-01-Rev2 Detector design specifications]] (Rev2: Added carrier board thickness recommendations) --- See also submitted article on design optimization&lt;br /&gt;
* [[:File:pCT-WP1-02-Rev3 (Radiation environment and electronics).pdf | pCT-WP1-02-Rev3 Radiation environment and placement of electronics]] (Rev2: Updated results and assumptions, Rev3: Updated with 1-10cm results) (Please feel free to contact [mailto:jars@hvl.no Jarle Rambo Sølie] if there are any questions regarding the contents of this document.&lt;br /&gt;
&lt;br /&gt;
==== Theses ====&lt;br /&gt;
* Daniel Aadnevik - MSc - 2014 - Extremely high-granularity digital tracking calorimeter for the detection of scattered protons in pCT&lt;br /&gt;
* [http://bora.uib.no/bitstream/handle/1956/10412/135279255.pdf?sequence=1&amp;amp;isAllowed=y Kristian Austreim - MSc - 2015 - Proton computed tomography readout testing and detector design]&lt;br /&gt;
* [http://bora.uib.no/bitstream/handle/1956/16041/thesis_final.pdf?sequence=1&amp;amp;isAllowed=y Ola Grøttvik - MSc - 2017 - Design of High-Speed Digital Readout System for Use in Proton Computed Tomography]&lt;br /&gt;
* [http://bora.uib.no/bitstream/handle/1956/16758/PCT_readout_testing_and_detector_HSchaug.pdf?sequence=1&amp;amp;isAllowed=y Håkon Schaug - MSc - 2017 - Proton Beam Test Of A High Granularity Calorimeter For Proton Computed Tomography]&lt;br /&gt;
* [https://brage.bibsys.no/xmlui/bitstream/handle/11250/2434108/16246_FULLTEXT.pdf?sequence=1&amp;amp;isAllowed=y Even Hansen - MSc - 2017 - Charge Diffusion Modelling for a Monolithic Active Pixel Sensor Detector with Application to Proton CT]&lt;br /&gt;
* [http://bora.uib.no/handle/1956/17757 Helge Pettersen - PhD - 2018 - A Digital Tracking Calorimeter for Proton Computed Tomography]&lt;br /&gt;
* [http://bora.uib.no/handle/1956/18748 Simon Kristian Huiberts - MSc - 2018 - Characterization of the ALPIDE chip using He ions (Data from Australian Micro beam, cluster size characteristics). ]&lt;br /&gt;
* [http://bora.uib.no/handle/1956/18058 Viljar Nilsen Ekeland - MSc - 2018 - Characterization of the ALPIDE chip using protons (Data from Oslo beam test, cluster size and LET correlation with different bias voltages).]&lt;br /&gt;
* [http://bora.uib.no/handle/1956/18057 Susmita Afroz - MSc - 2018 - Noise and Cluster Size Studies of ALPIDE-CMOS Pixel Sensor for pCT]&lt;br /&gt;
* [http://bora.uib.no/handle/1956/918/ H&amp;amp;aring;kon Andreas Underdal - MSc (HVL) - 2019 - Data Acquisition and Testing Software for a Proton Computed Tomography System  ]&lt;br /&gt;
* [http://bora.uib.no/handle/1956/20857  Silje Grimstad - MSc (HVL) - 2019 - ALPIDE Cluster simulations (Building database of cluster characteristics, simulation of clusters using said database. Position and cluster separation algorithms)].&lt;br /&gt;
* [http://resolver.tudelft.nl/uuid:e8d3f687-43ff-4d5f-a594-2e7d805f146b Alba Garcia Santos - MSc (Utrecht) - 2019 - Improvements of track reconstruction algorithms in pixel-based pCT calorimeters]&lt;br /&gt;
* [https://hdl.handle.net/1956/21101 Aleksei Kuleshov - MSc - 2019 - Proton CT monitoring and ALPIDE control (MQTT protocol server, System workflow, GUI implementation).]&lt;br /&gt;
* [https://bora.uib.no/bora-xmlui/handle/1956/24109 Øistein Jelmert Skjolddal - MSc (HVL) - 2020 Scalable Readout for Proton CT - pRU parser and Root interface.]&lt;br /&gt;
* [https://bora.uib.no/bora-xmlui/handle/11250/2716854 Jarle Rambo Sølie - PhD (HVL/UiB) - 2020 A Monte Carlo simulation framework for performance evaluation of a proton imaging system without front trackers.]&lt;br /&gt;
* [https://hdl.handle.net/11250/2725567 Ola Grøttvik - PhD (UiB) - 2021 Design and Implementation of a High-Speed Readout and Control System for a Digital Tracking Calorimeter for proton CT.]&lt;br /&gt;
* [https://hdl.handle.net/11250/2770399 Alf Kristoffer Herland - MSc (HVL) - 2021 Development and implementation of data acquisition software for proton computed tomography.]&lt;br /&gt;
&lt;br /&gt;
==== Journal Articles ====&lt;br /&gt;
* Alme, J., Barnaföldi, G.G., Barthel, R., Borshchov, V., Bodova, T., van den Brink, A., et al. &amp;lt;b&amp;gt;A High-Granularity Digital Tracking Calorimeter Optimized for Proton CT. &amp;lt;/b&amp;gt; &amp;lt;i&amp;gt;Frontiers in Physics.&amp;lt;/i&amp;gt;  2020;8(460). &lt;br /&gt;
** Published manuscript: [[Media:10.3389_fphy.2020.568243.pdf | PDF]]&lt;br /&gt;
** Frontiers link: [https://www.frontiersin.org/article/10.3389/fphy.2020.568243 doi:10.3389/fphy.2020.568243]&lt;br /&gt;
&lt;br /&gt;
* Pettersen, H.E.S., Volz, L., Sølie, J. R., Alme, J., Barnaföldi, G.G., Barthel, R. et al. &amp;lt;b&amp;gt;Helium Radiography with a Digital Tracking Calorimeter-a Monte Carlo Study for Secondary Track Rejection. &amp;lt;/b&amp;gt; &amp;lt;i&amp;gt; Phys. Med. Biol.&amp;lt;/i&amp;gt; 2021;66(3):035004. &lt;br /&gt;
** Published manuscript: [[Media: Pettersen_2021_Phys._Med._Biol._66_035004.pdf | PDF]]&lt;br /&gt;
** IOP Science link: [https://iopscience.iop.org/article/10.1088/1361-6560/abca03 doi:10.1088/1361-6560/abca03]&lt;br /&gt;
&lt;br /&gt;
* Sølie, J.R., Volz, L., Pettersen H.E.S., Piersimoni, P., Odland, O.H., Röhrich, D., et al. &amp;lt;b&amp;gt;Image quality of list-mode proton imaging without front trackers. &amp;lt;/b&amp;gt; &amp;lt;i&amp;gt; Phys. Med. Biol.&amp;lt;/i&amp;gt; 2020;65(13):135012. &lt;br /&gt;
** Published manuscript: [[Media: 10.1088_1361-6560_ab8.pdf | PDF]]&lt;br /&gt;
** IOP Science link: [https://iopscience.iop.org/article/10.1088/1361-6560/ab8ddb doi:10.1088/1361-6560/ab8ddb]&lt;br /&gt;
&lt;br /&gt;
* Tambave, G., Alme, J., Barnaföldi, G.G., Barthel, R., Van Den Brink, A., Brons, S., et al.&amp;lt;b&amp;gt; Characterization of monolithic CMOS pixel sensor chip with ion beams for application in particle computed tomography. &amp;lt;/b&amp;gt; &amp;lt;i&amp;gt; Nuclear Instruments and Methods in Physics Research Section A&amp;lt;/i&amp;gt; 2020;958:162626. &lt;br /&gt;
** Published manuscript: [[Media: Tambave-2020-Characterization-of-monolithic-cm.pdf| PDF]]&lt;br /&gt;
** Elsevier link: [https://www.sciencedirect.com/science/article/pii/S0168900219311258?via%3Dihub doi:10.1016/j.nima.2019.162626]&lt;br /&gt;
&lt;br /&gt;
* Pettersen, H.E.S., J. Alme, A. van den Brink, M. Chaar, D. Fehlker, I. Meric, O.H. Odland, et al. &amp;lt;b&amp;gt;Proton Tracking in a High-Granularity Digital Tracking Calorimeter for Proton CT Purposes&amp;lt;/b&amp;gt;.  &amp;lt;i&amp;gt;Nuclear Instruments and Methods in Physics Research A 860C, 51–61. doi:10.1016/j.nima.2017.02.007.&amp;lt;/i&amp;gt;&lt;br /&gt;
** Published manuscript: [[Media: 1-s2.0-S0168900217301882-main.pdf | PDF]]&lt;br /&gt;
** Elsevier link: [http://www.sciencedirect.com/science/article/pii/S0168900217301882 doi:10.1016/j.nima.2017.02.007]&lt;br /&gt;
** arXiv link: [https://arxiv.org/abs/1611.02031 arXiv:1611.02031]&lt;br /&gt;
&lt;br /&gt;
* Pettersen, H.E.S., Chaar, M., Meric, I., Odland, O.H., Sølie, J., Röhrich, D. &amp;lt;b&amp;gt;Accuracy of parameterized proton range models; a comparison&amp;lt;/b&amp;gt;. &amp;lt;i&amp;gt;Radiation Physics and Chemistry, 144 (C): 295-297 (2018). doi:10.1016/j.radphyschem.2017.08.02&amp;lt;/i&amp;gt;&lt;br /&gt;
** Published manuscript: [[Media: Comparison of different calculation methods of proton ranges.pdf | PDF]]&lt;br /&gt;
** Elsevier link: [http://www.sciencedirect.com/science/article/pii/S0969806X17303869?via%3Dihub 10.1016/j.radphyschem.2017.08.028]&lt;br /&gt;
** arXiv link: [https://arxiv.org/abs/1704.08854  arXiv:1704.08854]&lt;br /&gt;
&lt;br /&gt;
* Pettersen, H. E. S., and D. Röhrich. 2017. &amp;lt;b&amp;gt;Kreftbehandling Med Protonterapi Og Proton CT.&amp;lt;/b&amp;gt; &amp;lt;i&amp;gt;Fra Fysikkens Verden, December 2017.&amp;lt;/i&amp;gt;&lt;br /&gt;
** Published article: [[Media: FFV-proton-CT-ensidig.pdf | PDF]]&lt;br /&gt;
** [http://norskfysisk.no/filer/FFV/2017/FFV-2017-4.pdf Magazine at norskfysisk.no]&lt;br /&gt;
&lt;br /&gt;
==== In review ====&lt;br /&gt;
* Pettersen, H.E.S., Meric, I., Odland, O.H., Shafiee, H., Sølie, J., Röhrich, D. &amp;lt;b&amp;gt;Proton Tracking Algorithm for Pixel Based Range Telescopes for Proton Computed Tomography&amp;lt;/b&amp;gt;. &amp;lt;i&amp;gt;Revision submitted to Web of Conferences after the &amp;quot;Connecting the Dots&amp;quot; conference.&amp;lt;/i&amp;gt;&lt;br /&gt;
** Revised manuscript: [[Media: detector-proton-tracking.pdf | PDF]]&lt;br /&gt;
&lt;br /&gt;
* Pettersen, Helge Egil Seime, Lennart Volz, Jarle Sølie, Dieter Rohrich, and Joao Seco. &amp;lt;b&amp;gt;A Linear Projection Model to Estimate a Proton’s Position in a Pencil Beam For Single Sided Proton Imaging,&amp;lt;/b&amp;gt;. &amp;lt;i&amp;gt;Submitted to Physics in Medicine and Biology.&amp;lt;/i&amp;gt;&lt;br /&gt;
** Submitted manuscript: [[Media: Authors manuscript.pdf | PDF]]&lt;br /&gt;
&lt;br /&gt;
* Pettersen, Helge Egil Seime, Johan Alme, Gergely Gabor Barnafoldi, Alba Garcıa-Santos, Ola Grøttvik, Håvard Helstrup, Kristin Fanebust Hetland, Ilker Meric, Odd Harald Odland, Gabor Papp, Thomas Peitzmann, Dieter Röhrich, Joao Seco, Hesam Shafiee, Eivind Vågslid Skjæveland, Ganesh Tambave, Kjetil Ullaland, Monika Varga-Kofarago, Lennart Volz, Boris Wagner and Shiming Yang. &amp;lt;b&amp;gt;Design Optimization of a Pixel Based Range Telescope for Proton Computed Tomography.&amp;lt;/b&amp;gt; &amp;lt;i&amp;gt;Submitted to Physica Medica Special Issue: Advances in Geant4 for medicine.&amp;lt;/i&amp;gt;&lt;br /&gt;
** Submitted manuscript: [[Media: Pettersen et al. - Design Optimization of a Pixel Based Range Telesco.pdf| PDF]]&lt;br /&gt;
&lt;br /&gt;
* Eikeland, Viljar Nilsen et al. &amp;lt;b&amp;gt; Bergen Proton CT System. &amp;lt;/b&amp;gt; &amp;lt;i&amp;gt; Submitted as proceedings for the 12th Position Sensitive Detectors conference. &amp;lt;/i&amp;gt;&lt;br /&gt;
** Submitted manuscript: [[Media: psd_proceedings.pdf | PDF]]&lt;br /&gt;
&lt;br /&gt;
==== Posters ====&lt;br /&gt;
* Eikeland, Viljar Nilsen. &amp;lt;b&amp;gt; Bergen proton CT system. &amp;lt;/b&amp;gt; &amp;lt;i&amp;gt; Presented at the 12th Position Sensitive Detectors conference.&amp;lt;/i&amp;gt; &lt;br /&gt;
** Submitted poster [[Media: poster_PSD12.pdf | PDF]]&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
==== Work in Progress ====&lt;br /&gt;
* J. Sølie, H. E. S. Pettersen, I. Meric, O. H. Odland, H. Helstrup and D. Röhrich: &amp;lt;b&amp;gt;A comparison of longitudinal and lateral range for protons traversing complex media using GATE, MCNP6 and FLUKA Monte Carlo simulations.&amp;lt;/b&amp;gt;&lt;br /&gt;
&lt;br /&gt;
== Meetings ==&lt;br /&gt;
Hosted on Indico  https://indico.cern.ch/category/13882.&lt;br /&gt;
&lt;br /&gt;
The old pages on the wiki can be found here: [[Meetings]]&lt;br /&gt;
&lt;br /&gt;
Slides from the project [[Workshops | workshops in 2016]]&lt;br /&gt;
&lt;br /&gt;
== [[Commissioning]] ==&lt;br /&gt;
Planning and information on [[Commissioning | commissioning, beam tests, etc]].&lt;br /&gt;
&lt;br /&gt;
== [[Workpackages]] ==&lt;br /&gt;
Sections for the different [[Workpackages | work packages]]&lt;br /&gt;
&lt;br /&gt;
== [[People]] ==&lt;br /&gt;
Contact info of involved people &lt;br /&gt;
&lt;br /&gt;
== [[Links]] ==&lt;br /&gt;
Link collection of topics regarding the project&lt;br /&gt;
&lt;br /&gt;
== Getting started ==&lt;br /&gt;
* Note: ASK is a placeholder that marks questions &lt;br /&gt;
* Note: Search function is not ideal. It doesn&#039;t find all occurences of the search term, e.g. aries finds libraries but not aries.bccs&lt;br /&gt;
&lt;br /&gt;
* Consult the [//meta.wikimedia.org/wiki/Help:Contents User&#039;s Guide] for information on using the wiki software.&lt;br /&gt;
* [//www.mediawiki.org/wiki/Manual:Configuration_settings Configuration settings list]&lt;br /&gt;
* [//www.mediawiki.org/wiki/Manual:FAQ MediaWiki FAQ]&lt;br /&gt;
* [https://lists.wikimedia.org/mailman/listinfo/mediawiki-announce MediaWiki release mailing list]&lt;/div&gt;</summary>
		<author><name>Xej010</name></author>
	</entry>
	<entry>
		<id>https://pct.wiki.uib.no/index.php?title=Main_Page&amp;diff=995</id>
		<title>Main Page</title>
		<link rel="alternate" type="text/html" href="https://pct.wiki.uib.no/index.php?title=Main_Page&amp;diff=995"/>
		<updated>2023-08-23T11:32:35Z</updated>

		<summary type="html">&lt;p&gt;Xej010: Documentation and Howto&amp;#039;s cleanup and added Århus Testbeam 2023&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;&#039;&#039;&#039;Wiki for the proton CT project&#039;&#039;&#039;&lt;br /&gt;
&lt;br /&gt;
== Documentation and Howto&#039;s ==&lt;br /&gt;
=== [[Software]] ===&lt;br /&gt;
* [[Documentation|Software Documentation]] on how to install and use the involved software packages, how to use the GitLab service, and about the development workflow, etc.&lt;br /&gt;
&lt;br /&gt;
=== [[Hardware ]] ===&lt;br /&gt;
* [[Hardware Documentation and Howto&#039;s]]&lt;br /&gt;
&lt;br /&gt;
=== [[Control &amp;amp; Readout Software ]] ===&lt;br /&gt;
* [[Control &amp;amp; Readout Software Documentation and Howto&#039;s]]&lt;br /&gt;
&lt;br /&gt;
=== [[ALPIDE]] ===&lt;br /&gt;
* [[ALPIDE Documentation and Papers]]&lt;br /&gt;
&lt;br /&gt;
=== [[Århus Testbeam 2023]] ===&lt;br /&gt;
&lt;br /&gt;
== [[Publications]] ==&lt;br /&gt;
List of publications from the project.&lt;br /&gt;
&lt;br /&gt;
==== Workpackage Reports ====&lt;br /&gt;
* [[Media:pCT-WP1-1-Rev2 design recommendations.pdf | pCT-WP1-01-Rev2 Detector design specifications]] (Rev2: Added carrier board thickness recommendations) --- See also submitted article on design optimization&lt;br /&gt;
* [[:File:pCT-WP1-02-Rev3 (Radiation environment and electronics).pdf | pCT-WP1-02-Rev3 Radiation environment and placement of electronics]] (Rev2: Updated results and assumptions, Rev3: Updated with 1-10cm results) (Please feel free to contact [mailto:jars@hvl.no Jarle Rambo Sølie] if there are any questions regarding the contents of this document.&lt;br /&gt;
&lt;br /&gt;
==== Theses ====&lt;br /&gt;
* Daniel Aadnevik - MSc - 2014 - Extremely high-granularity digital tracking calorimeter for the detection of scattered protons in pCT&lt;br /&gt;
* [http://bora.uib.no/bitstream/handle/1956/10412/135279255.pdf?sequence=1&amp;amp;isAllowed=y Kristian Austreim - MSc - 2015 - Proton computed tomography readout testing and detector design]&lt;br /&gt;
* [http://bora.uib.no/bitstream/handle/1956/16041/thesis_final.pdf?sequence=1&amp;amp;isAllowed=y Ola Grøttvik - MSc - 2017 - Design of High-Speed Digital Readout System for Use in Proton Computed Tomography]&lt;br /&gt;
* [http://bora.uib.no/bitstream/handle/1956/16758/PCT_readout_testing_and_detector_HSchaug.pdf?sequence=1&amp;amp;isAllowed=y Håkon Schaug - MSc - 2017 - Proton Beam Test Of A High Granularity Calorimeter For Proton Computed Tomography]&lt;br /&gt;
* [https://brage.bibsys.no/xmlui/bitstream/handle/11250/2434108/16246_FULLTEXT.pdf?sequence=1&amp;amp;isAllowed=y Even Hansen - MSc - 2017 - Charge Diffusion Modelling for a Monolithic Active Pixel Sensor Detector with Application to Proton CT]&lt;br /&gt;
* [http://bora.uib.no/handle/1956/17757 Helge Pettersen - PhD - 2018 - A Digital Tracking Calorimeter for Proton Computed Tomography]&lt;br /&gt;
* [http://bora.uib.no/handle/1956/18748 Simon Kristian Huiberts - MSc - 2018 - Characterization of the ALPIDE chip using He ions (Data from Australian Micro beam, cluster size characteristics). ]&lt;br /&gt;
* [http://bora.uib.no/handle/1956/18058 Viljar Nilsen Ekeland - MSc - 2018 - Characterization of the ALPIDE chip using protons (Data from Oslo beam test, cluster size and LET correlation with different bias voltages).]&lt;br /&gt;
* [http://bora.uib.no/handle/1956/18057 Susmita Afroz - MSc - 2018 - Noise and Cluster Size Studies of ALPIDE-CMOS Pixel Sensor for pCT]&lt;br /&gt;
* [http://bora.uib.no/handle/1956/918/ H&amp;amp;aring;kon Andreas Underdal - MSc (HVL) - 2019 - Data Acquisition and Testing Software for a Proton Computed Tomography System  ]&lt;br /&gt;
* [http://bora.uib.no/handle/1956/20857  Silje Grimstad - MSc (HVL) - 2019 - ALPIDE Cluster simulations (Building database of cluster characteristics, simulation of clusters using said database. Position and cluster separation algorithms)].&lt;br /&gt;
* [http://resolver.tudelft.nl/uuid:e8d3f687-43ff-4d5f-a594-2e7d805f146b Alba Garcia Santos - MSc (Utrecht) - 2019 - Improvements of track reconstruction algorithms in pixel-based pCT calorimeters]&lt;br /&gt;
* [https://hdl.handle.net/1956/21101 Aleksei Kuleshov - MSc - 2019 - Proton CT monitoring and ALPIDE control (MQTT protocol server, System workflow, GUI implementation).]&lt;br /&gt;
* [https://bora.uib.no/bora-xmlui/handle/1956/24109 Øistein Jelmert Skjolddal - MSc (HVL) - 2020 Scalable Readout for Proton CT - pRU parser and Root interface.]&lt;br /&gt;
* [https://bora.uib.no/bora-xmlui/handle/11250/2716854 Jarle Rambo Sølie - PhD (HVL/UiB) - 2020 A Monte Carlo simulation framework for performance evaluation of a proton imaging system without front trackers.]&lt;br /&gt;
* [https://hdl.handle.net/11250/2725567 Ola Grøttvik - PhD (UiB) - 2021 Design and Implementation of a High-Speed Readout and Control System for a Digital Tracking Calorimeter for proton CT.]&lt;br /&gt;
* [https://hdl.handle.net/11250/2770399 Alf Kristoffer Herland - MSc (HVL) - 2021 Development and implementation of data acquisition software for proton computed tomography.]&lt;br /&gt;
&lt;br /&gt;
==== Journal Articles ====&lt;br /&gt;
* Alme, J., Barnaföldi, G.G., Barthel, R., Borshchov, V., Bodova, T., van den Brink, A., et al. &amp;lt;b&amp;gt;A High-Granularity Digital Tracking Calorimeter Optimized for Proton CT. &amp;lt;/b&amp;gt; &amp;lt;i&amp;gt;Frontiers in Physics.&amp;lt;/i&amp;gt;  2020;8(460). &lt;br /&gt;
** Published manuscript: [[Media:10.3389_fphy.2020.568243.pdf | PDF]]&lt;br /&gt;
** Frontiers link: [https://www.frontiersin.org/article/10.3389/fphy.2020.568243 doi:10.3389/fphy.2020.568243]&lt;br /&gt;
&lt;br /&gt;
* Pettersen, H.E.S., Volz, L., Sølie, J. R., Alme, J., Barnaföldi, G.G., Barthel, R. et al. &amp;lt;b&amp;gt;Helium Radiography with a Digital Tracking Calorimeter-a Monte Carlo Study for Secondary Track Rejection. &amp;lt;/b&amp;gt; &amp;lt;i&amp;gt; Phys. Med. Biol.&amp;lt;/i&amp;gt; 2021;66(3):035004. &lt;br /&gt;
** Published manuscript: [[Media: Pettersen_2021_Phys._Med._Biol._66_035004.pdf | PDF]]&lt;br /&gt;
** IOP Science link: [https://iopscience.iop.org/article/10.1088/1361-6560/abca03 doi:10.1088/1361-6560/abca03]&lt;br /&gt;
&lt;br /&gt;
* Sølie, J.R., Volz, L., Pettersen H.E.S., Piersimoni, P., Odland, O.H., Röhrich, D., et al. &amp;lt;b&amp;gt;Image quality of list-mode proton imaging without front trackers. &amp;lt;/b&amp;gt; &amp;lt;i&amp;gt; Phys. Med. Biol.&amp;lt;/i&amp;gt; 2020;65(13):135012. &lt;br /&gt;
** Published manuscript: [[Media: 10.1088_1361-6560_ab8.pdf | PDF]]&lt;br /&gt;
** IOP Science link: [https://iopscience.iop.org/article/10.1088/1361-6560/ab8ddb doi:10.1088/1361-6560/ab8ddb]&lt;br /&gt;
&lt;br /&gt;
* Tambave, G., Alme, J., Barnaföldi, G.G., Barthel, R., Van Den Brink, A., Brons, S., et al.&amp;lt;b&amp;gt; Characterization of monolithic CMOS pixel sensor chip with ion beams for application in particle computed tomography. &amp;lt;/b&amp;gt; &amp;lt;i&amp;gt; Nuclear Instruments and Methods in Physics Research Section A&amp;lt;/i&amp;gt; 2020;958:162626. &lt;br /&gt;
** Published manuscript: [[Media: Tambave-2020-Characterization-of-monolithic-cm.pdf| PDF]]&lt;br /&gt;
** Elsevier link: [https://www.sciencedirect.com/science/article/pii/S0168900219311258?via%3Dihub doi:10.1016/j.nima.2019.162626]&lt;br /&gt;
&lt;br /&gt;
* Pettersen, H.E.S., J. Alme, A. van den Brink, M. Chaar, D. Fehlker, I. Meric, O.H. Odland, et al. &amp;lt;b&amp;gt;Proton Tracking in a High-Granularity Digital Tracking Calorimeter for Proton CT Purposes&amp;lt;/b&amp;gt;.  &amp;lt;i&amp;gt;Nuclear Instruments and Methods in Physics Research A 860C, 51–61. doi:10.1016/j.nima.2017.02.007.&amp;lt;/i&amp;gt;&lt;br /&gt;
** Published manuscript: [[Media: 1-s2.0-S0168900217301882-main.pdf | PDF]]&lt;br /&gt;
** Elsevier link: [http://www.sciencedirect.com/science/article/pii/S0168900217301882 doi:10.1016/j.nima.2017.02.007]&lt;br /&gt;
** arXiv link: [https://arxiv.org/abs/1611.02031 arXiv:1611.02031]&lt;br /&gt;
&lt;br /&gt;
* Pettersen, H.E.S., Chaar, M., Meric, I., Odland, O.H., Sølie, J., Röhrich, D. &amp;lt;b&amp;gt;Accuracy of parameterized proton range models; a comparison&amp;lt;/b&amp;gt;. &amp;lt;i&amp;gt;Radiation Physics and Chemistry, 144 (C): 295-297 (2018). doi:10.1016/j.radphyschem.2017.08.02&amp;lt;/i&amp;gt;&lt;br /&gt;
** Published manuscript: [[Media: Comparison of different calculation methods of proton ranges.pdf | PDF]]&lt;br /&gt;
** Elsevier link: [http://www.sciencedirect.com/science/article/pii/S0969806X17303869?via%3Dihub 10.1016/j.radphyschem.2017.08.028]&lt;br /&gt;
** arXiv link: [https://arxiv.org/abs/1704.08854  arXiv:1704.08854]&lt;br /&gt;
&lt;br /&gt;
* Pettersen, H. E. S., and D. Röhrich. 2017. &amp;lt;b&amp;gt;Kreftbehandling Med Protonterapi Og Proton CT.&amp;lt;/b&amp;gt; &amp;lt;i&amp;gt;Fra Fysikkens Verden, December 2017.&amp;lt;/i&amp;gt;&lt;br /&gt;
** Published article: [[Media: FFV-proton-CT-ensidig.pdf | PDF]]&lt;br /&gt;
** [http://norskfysisk.no/filer/FFV/2017/FFV-2017-4.pdf Magazine at norskfysisk.no]&lt;br /&gt;
&lt;br /&gt;
==== In review ====&lt;br /&gt;
* Pettersen, H.E.S., Meric, I., Odland, O.H., Shafiee, H., Sølie, J., Röhrich, D. &amp;lt;b&amp;gt;Proton Tracking Algorithm for Pixel Based Range Telescopes for Proton Computed Tomography&amp;lt;/b&amp;gt;. &amp;lt;i&amp;gt;Revision submitted to Web of Conferences after the &amp;quot;Connecting the Dots&amp;quot; conference.&amp;lt;/i&amp;gt;&lt;br /&gt;
** Revised manuscript: [[Media: detector-proton-tracking.pdf | PDF]]&lt;br /&gt;
&lt;br /&gt;
* Pettersen, Helge Egil Seime, Lennart Volz, Jarle Sølie, Dieter Rohrich, and Joao Seco. &amp;lt;b&amp;gt;A Linear Projection Model to Estimate a Proton’s Position in a Pencil Beam For Single Sided Proton Imaging,&amp;lt;/b&amp;gt;. &amp;lt;i&amp;gt;Submitted to Physics in Medicine and Biology.&amp;lt;/i&amp;gt;&lt;br /&gt;
** Submitted manuscript: [[Media: Authors manuscript.pdf | PDF]]&lt;br /&gt;
&lt;br /&gt;
* Pettersen, Helge Egil Seime, Johan Alme, Gergely Gabor Barnafoldi, Alba Garcıa-Santos, Ola Grøttvik, Håvard Helstrup, Kristin Fanebust Hetland, Ilker Meric, Odd Harald Odland, Gabor Papp, Thomas Peitzmann, Dieter Röhrich, Joao Seco, Hesam Shafiee, Eivind Vågslid Skjæveland, Ganesh Tambave, Kjetil Ullaland, Monika Varga-Kofarago, Lennart Volz, Boris Wagner and Shiming Yang. &amp;lt;b&amp;gt;Design Optimization of a Pixel Based Range Telescope for Proton Computed Tomography.&amp;lt;/b&amp;gt; &amp;lt;i&amp;gt;Submitted to Physica Medica Special Issue: Advances in Geant4 for medicine.&amp;lt;/i&amp;gt;&lt;br /&gt;
** Submitted manuscript: [[Media: Pettersen et al. - Design Optimization of a Pixel Based Range Telesco.pdf| PDF]]&lt;br /&gt;
&lt;br /&gt;
* Eikeland, Viljar Nilsen et al. &amp;lt;b&amp;gt; Bergen Proton CT System. &amp;lt;/b&amp;gt; &amp;lt;i&amp;gt; Submitted as proceedings for the 12th Position Sensitive Detectors conference. &amp;lt;/i&amp;gt;&lt;br /&gt;
** Submitted manuscript: [[Media: psd_proceedings.pdf | PDF]]&lt;br /&gt;
&lt;br /&gt;
==== Posters ====&lt;br /&gt;
* Eikeland, Viljar Nilsen. &amp;lt;b&amp;gt; Bergen proton CT system. &amp;lt;/b&amp;gt; &amp;lt;i&amp;gt; Presented at the 12th Position Sensitive Detectors conference.&amp;lt;/i&amp;gt; &lt;br /&gt;
** Submitted poster [[Media: poster_PSD12.pdf | PDF]]&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
==== Work in Progress ====&lt;br /&gt;
* J. Sølie, H. E. S. Pettersen, I. Meric, O. H. Odland, H. Helstrup and D. Röhrich: &amp;lt;b&amp;gt;A comparison of longitudinal and lateral range for protons traversing complex media using GATE, MCNP6 and FLUKA Monte Carlo simulations.&amp;lt;/b&amp;gt;&lt;br /&gt;
&lt;br /&gt;
== Meetings ==&lt;br /&gt;
Hosted on Indico  https://indico.cern.ch/category/13882.&lt;br /&gt;
&lt;br /&gt;
The old pages on the wiki can be found here: [[Meetings]]&lt;br /&gt;
&lt;br /&gt;
Slides from the project [[Workshops | workshops in 2016]]&lt;br /&gt;
&lt;br /&gt;
== [[Commissioning]] ==&lt;br /&gt;
Planning and information on [[Commissioning | commissioning, beam tests, etc]].&lt;br /&gt;
&lt;br /&gt;
== [[Workpackages]] ==&lt;br /&gt;
Sections for the different [[Workpackages | work packages]]&lt;br /&gt;
&lt;br /&gt;
== [[People]] ==&lt;br /&gt;
Contact info of involved people &lt;br /&gt;
&lt;br /&gt;
== [[Links]] ==&lt;br /&gt;
Link collection of topics regarding the project&lt;br /&gt;
&lt;br /&gt;
== Getting started ==&lt;br /&gt;
* Note: ASK is a placeholder that marks questions &lt;br /&gt;
* Note: Search function is not ideal. It doesn&#039;t find all occurences of the search term, e.g. aries finds libraries but not aries.bccs&lt;br /&gt;
&lt;br /&gt;
* Consult the [//meta.wikimedia.org/wiki/Help:Contents User&#039;s Guide] for information on using the wiki software.&lt;br /&gt;
* [//www.mediawiki.org/wiki/Manual:Configuration_settings Configuration settings list]&lt;br /&gt;
* [//www.mediawiki.org/wiki/Manual:FAQ MediaWiki FAQ]&lt;br /&gt;
* [https://lists.wikimedia.org/mailman/listinfo/mediawiki-announce MediaWiki release mailing list]&lt;/div&gt;</summary>
		<author><name>Xej010</name></author>
	</entry>
	<entry>
		<id>https://pct.wiki.uib.no/index.php?title=Hardware_Documentation_and_Howto%27s&amp;diff=994</id>
		<title>Hardware Documentation and Howto&#039;s</title>
		<link rel="alternate" type="text/html" href="https://pct.wiki.uib.no/index.php?title=Hardware_Documentation_and_Howto%27s&amp;diff=994"/>
		<updated>2022-06-21T08:31:38Z</updated>

		<summary type="html">&lt;p&gt;Xej010: /* Cooling Laboratory Setup */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;[[Main Page]] -&amp;gt; [[Hardware Documentation and Howto&#039;s]]&lt;br /&gt;
&lt;br /&gt;
== Getting Started ==&lt;br /&gt;
&lt;br /&gt;
* [[Getting Started VCU118|VCU118]]&lt;br /&gt;
* [[Getting Started PTB|PTB]]&lt;br /&gt;
&lt;br /&gt;
== Documentation ==&lt;br /&gt;
&lt;br /&gt;
=== pRU ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Clock_network.png | pRU Clock Network]]&lt;br /&gt;
* [[:Media:PRU Address Map.pdf | pRU Address Map]]&lt;br /&gt;
* [[:Media:PRU Ethernet Configurations.pdf | DCS and Data Offload Ethernet Configurations]]&lt;br /&gt;
* [[:Media:PDTP.pdf | pCT Data Transfer Protocol]]&lt;br /&gt;
* [[:Media:Data format v0.2.pdf | pRU Data Format]]&lt;br /&gt;
* [[:Media:FpgaCalc.ods | FPGA and ALPIDE radiation calculations]]&lt;br /&gt;
* [[:Media:Control Interface.pdf | pRU Control Interface]] [Deprecated, only in use on PTB. Replaced with IPBus on VCU118 + all other boards in the future.]&lt;br /&gt;
&lt;br /&gt;
==== pRU Registers and Bus System ====&lt;br /&gt;
[[File:Top level firmware.png|500px]][[File:Bus tree.png|500px]]&lt;br /&gt;
&lt;br /&gt;
The pRU bus system is connecting the various modules on the FPGA to a common master, the Microblaze Subsystem.&lt;br /&gt;
Each of the modules is associated with a given BASE-ADDRESS specified in the [[:Media:Control Interface.pdf | pRU Control Interface Document]].&lt;br /&gt;
Note that several instances do exist for certain modules. E.g. there are one alpide_data instance for each ALPIDE chip connected to the pRU.&lt;br /&gt;
To communicate with a specific instance one needs to add an offset of 0x1000 times the instance number to the module base address.&lt;br /&gt;
&lt;br /&gt;
E.g. if you want to communicate with the &lt;br /&gt;
&lt;br /&gt;
* 1st instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt;&lt;br /&gt;
&lt;br /&gt;
* 2nd instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt; + (0x1000 * (2-1))&lt;br /&gt;
&lt;br /&gt;
* 16th instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt; + (0x1000 * (16-1))&lt;br /&gt;
&lt;br /&gt;
===== Module Registers =====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Global_regs.pdf | global_regs]]&lt;br /&gt;
* [[:Media:Trigger_manager.pdf | trigger_manager]]&lt;br /&gt;
* [[:Media:Offload.pdf | offload]]&lt;br /&gt;
* [[:Media:Alpide_control.pdf | alpide_control]]&lt;br /&gt;
* [[:Media:Alpide_data.pdf | alpide_data]]&lt;br /&gt;
&lt;br /&gt;
==== PTB-specific Module Registers ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Power_control.pdf | power_control]]&lt;br /&gt;
* [[:Media:Ptb_regs.pdf | ptb_regs]]&lt;br /&gt;
&lt;br /&gt;
=== Transition Card (TC) ===&lt;br /&gt;
&lt;br /&gt;
*  [[Media:TC-v1.0_schematic.pdf | TC-v1.0 Schematic]]&lt;br /&gt;
&lt;br /&gt;
=== ALPIDE Chip ===&lt;br /&gt;
&lt;br /&gt;
* [[Media:Alpide manual ver3.pdf | ALPIDE Manual v0.3]]&lt;br /&gt;
&lt;br /&gt;
=== ALPIDE Bonding and Mounting ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Report_Feb_2019.pdf | 9-chip String Simulation - and proposed 9-chip string redesign - 2019 Feb ]]&lt;br /&gt;
&lt;br /&gt;
==== Chip Cable ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:2020_01_08.zip | 2020 January 8 ]]&lt;br /&gt;
* [[:Media:2019_05_16.zip | 2019 May 16 (ULTM)]]&lt;br /&gt;
&lt;br /&gt;
==== 9 Chip String ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:2019_11_05.zip | 2019 November 5 ]]&lt;br /&gt;
* Some of the aluminium traces on the flex cable broke by the tail of the cable (near the ZIF stiffener). [[Media:Tail_modifications.png | Current design and possible modifications]] shows the current design and two possible modifications. It has been decided that new designs will use the &#039;&#039;&#039;design 1 modification&#039;&#039;&#039; and &#039;&#039;&#039;longer ZIF-stiffener&#039;&#039;&#039; (30 mm long).&lt;br /&gt;
&lt;br /&gt;
=== Production Test Box (PTB) ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:PTB-v1.0_schematic.pdf | PTB-v1.0 Schematic]]&lt;br /&gt;
* [[:Media:PTB-v1.0_samtec.zip | PTB-v1.0 FPGA Connections]]&lt;br /&gt;
* [[:Media:PTB-v1.0_yamaichi.zip | PTB-v1.0 Yamaichi Connections]]&lt;br /&gt;
&lt;br /&gt;
=== FPGA Mezzanine Card (FMC) ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:FMC-v1.0_schematic.pdf | FMC-v1.0 Schematic]]&lt;br /&gt;
&lt;br /&gt;
=== mTower ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:mTower_schematic.pdf | mTower Schematic]]&lt;br /&gt;
&lt;br /&gt;
=== Cooling Laboratory Setup ===&lt;br /&gt;
&lt;br /&gt;
1x LAUDA Ultracool UC 4 is used for water cooling in the laboratory now ([https://www.lauda.de/pim/datasheet/LAUDA_UC4_E6004411_en_20211220_135424.pdf data sheet] and [https://cdn.accentuate.io/6800432890013/1624628180288/DMI-0210-01_UC_2-4__EN_.pdf?v=0 manual]).&lt;br /&gt;
&lt;br /&gt;
1x Digital flow switch with temperature sensor for the cold plate (flow rate 13,6 l/min) SMC PF3W520S-04-2T-R-X128 &lt;br /&gt;
&lt;br /&gt;
1x Digital flow switch with temperature sensor for the tracking layers (flow rate 3,2 l/min) SMC PF3W504S-03-2T-R-X128 &lt;br /&gt;
&lt;br /&gt;
2x Digital flow monitor (SMC PFG310-SV)&lt;br /&gt;
&lt;br /&gt;
4x Meas Heavy Industrial Pressure Transmitter (M5131-70010X-004BC)&lt;br /&gt;
&lt;br /&gt;
3x Axial fans 4-wire 12V&lt;br /&gt;
&lt;br /&gt;
1x I/O Module Moxa ioLogik E1212 (8x digital inputs, 8x digital inputs/outputs)&lt;br /&gt;
&lt;br /&gt;
1x I/O Module Moxa ioLogik E1240 (8x analog inputs)&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Moxa-iologik-e1200-series-manual-v15.10.pdf | Moxa E1200 Series manual]]&lt;br /&gt;
* [[:Media:Moxa-iologik-e1200-series-datasheet-v2.3.pdf | Moxa E1200 Series datasheet]]&lt;br /&gt;
* [[:Media:PCT_lab_setup.pdf | Schematic of the pCT lab setup]]&lt;/div&gt;</summary>
		<author><name>Xej010</name></author>
	</entry>
	<entry>
		<id>https://pct.wiki.uib.no/index.php?title=File:Moxa-iologik-e1200-series-datasheet-v2.3.pdf&amp;diff=993</id>
		<title>File:Moxa-iologik-e1200-series-datasheet-v2.3.pdf</title>
		<link rel="alternate" type="text/html" href="https://pct.wiki.uib.no/index.php?title=File:Moxa-iologik-e1200-series-datasheet-v2.3.pdf&amp;diff=993"/>
		<updated>2022-06-21T08:29:10Z</updated>

		<summary type="html">&lt;p&gt;Xej010: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;&lt;/div&gt;</summary>
		<author><name>Xej010</name></author>
	</entry>
	<entry>
		<id>https://pct.wiki.uib.no/index.php?title=File:Moxa-iologik-e1200-series-manual-v15.10.pdf&amp;diff=992</id>
		<title>File:Moxa-iologik-e1200-series-manual-v15.10.pdf</title>
		<link rel="alternate" type="text/html" href="https://pct.wiki.uib.no/index.php?title=File:Moxa-iologik-e1200-series-manual-v15.10.pdf&amp;diff=992"/>
		<updated>2022-06-21T08:28:53Z</updated>

		<summary type="html">&lt;p&gt;Xej010: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;&lt;/div&gt;</summary>
		<author><name>Xej010</name></author>
	</entry>
	<entry>
		<id>https://pct.wiki.uib.no/index.php?title=File:PCT_lab_setup.pdf&amp;diff=991</id>
		<title>File:PCT lab setup.pdf</title>
		<link rel="alternate" type="text/html" href="https://pct.wiki.uib.no/index.php?title=File:PCT_lab_setup.pdf&amp;diff=991"/>
		<updated>2022-04-19T14:32:23Z</updated>

		<summary type="html">&lt;p&gt;Xej010: Xej010 uploaded a new version of File:PCT lab setup.pdf&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;&lt;/div&gt;</summary>
		<author><name>Xej010</name></author>
	</entry>
	<entry>
		<id>https://pct.wiki.uib.no/index.php?title=File:PCT_lab_setup.pdf&amp;diff=990</id>
		<title>File:PCT lab setup.pdf</title>
		<link rel="alternate" type="text/html" href="https://pct.wiki.uib.no/index.php?title=File:PCT_lab_setup.pdf&amp;diff=990"/>
		<updated>2022-04-19T14:27:17Z</updated>

		<summary type="html">&lt;p&gt;Xej010: Xej010 uploaded a new version of File:PCT lab setup.pdf&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;&lt;/div&gt;</summary>
		<author><name>Xej010</name></author>
	</entry>
	<entry>
		<id>https://pct.wiki.uib.no/index.php?title=Hardware_Documentation_and_Howto%27s&amp;diff=988</id>
		<title>Hardware Documentation and Howto&#039;s</title>
		<link rel="alternate" type="text/html" href="https://pct.wiki.uib.no/index.php?title=Hardware_Documentation_and_Howto%27s&amp;diff=988"/>
		<updated>2022-04-13T13:13:08Z</updated>

		<summary type="html">&lt;p&gt;Xej010: /* Cooling Laboratory Setup */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;[[Main Page]] -&amp;gt; [[Hardware Documentation and Howto&#039;s]]&lt;br /&gt;
&lt;br /&gt;
== Getting Started ==&lt;br /&gt;
&lt;br /&gt;
* [[Getting Started VCU118|VCU118]]&lt;br /&gt;
* [[Getting Started PTB|PTB]]&lt;br /&gt;
&lt;br /&gt;
== Documentation ==&lt;br /&gt;
&lt;br /&gt;
=== pRU ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Clock_network.png | pRU Clock Network]]&lt;br /&gt;
* [[:Media:PRU Address Map.pdf | pRU Address Map]]&lt;br /&gt;
* [[:Media:PRU Ethernet Configurations.pdf | DCS and Data Offload Ethernet Configurations]]&lt;br /&gt;
* [[:Media:PDTP.pdf | pCT Data Transfer Protocol]]&lt;br /&gt;
* [[:Media:Data format v0.2.pdf | pRU Data Format]]&lt;br /&gt;
* [[:Media:FpgaCalc.ods | FPGA and ALPIDE radiation calculations]]&lt;br /&gt;
* [[:Media:Control Interface.pdf | pRU Control Interface]] [Deprecated, only in use on PTB. Replaced with IPBus on VCU118 + all other boards in the future.]&lt;br /&gt;
&lt;br /&gt;
==== pRU Registers and Bus System ====&lt;br /&gt;
[[File:Top level firmware.png|500px]][[File:Bus tree.png|500px]]&lt;br /&gt;
&lt;br /&gt;
The pRU bus system is connecting the various modules on the FPGA to a common master, the Microblaze Subsystem.&lt;br /&gt;
Each of the modules is associated with a given BASE-ADDRESS specified in the [[:Media:Control Interface.pdf | pRU Control Interface Document]].&lt;br /&gt;
Note that several instances do exist for certain modules. E.g. there are one alpide_data instance for each ALPIDE chip connected to the pRU.&lt;br /&gt;
To communicate with a specific instance one needs to add an offset of 0x1000 times the instance number to the module base address.&lt;br /&gt;
&lt;br /&gt;
E.g. if you want to communicate with the &lt;br /&gt;
&lt;br /&gt;
* 1st instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt;&lt;br /&gt;
&lt;br /&gt;
* 2nd instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt; + (0x1000 * (2-1))&lt;br /&gt;
&lt;br /&gt;
* 16th instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt; + (0x1000 * (16-1))&lt;br /&gt;
&lt;br /&gt;
===== Module Registers =====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Global_regs.pdf | global_regs]]&lt;br /&gt;
* [[:Media:Trigger_manager.pdf | trigger_manager]]&lt;br /&gt;
* [[:Media:Offload.pdf | offload]]&lt;br /&gt;
* [[:Media:Alpide_control.pdf | alpide_control]]&lt;br /&gt;
* [[:Media:Alpide_data.pdf | alpide_data]]&lt;br /&gt;
&lt;br /&gt;
==== PTB-specific Module Registers ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Power_control.pdf | power_control]]&lt;br /&gt;
* [[:Media:Ptb_regs.pdf | ptb_regs]]&lt;br /&gt;
&lt;br /&gt;
=== Transition Card (TC) ===&lt;br /&gt;
&lt;br /&gt;
*  [[Media:TC-v1.0_schematic.pdf | TC-v1.0 Schematic]]&lt;br /&gt;
&lt;br /&gt;
=== ALPIDE Chip ===&lt;br /&gt;
&lt;br /&gt;
* [[Media:Alpide manual ver3.pdf | ALPIDE Manual v0.3]]&lt;br /&gt;
&lt;br /&gt;
=== ALPIDE Bonding and Mounting ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Report_Feb_2019.pdf | 9-chip String Simulation - and proposed 9-chip string redesign - 2019 Feb ]]&lt;br /&gt;
&lt;br /&gt;
==== Chip Cable ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:2020_01_08.zip | 2020 January 8 ]]&lt;br /&gt;
* [[:Media:2019_05_16.zip | 2019 May 16 (ULTM)]]&lt;br /&gt;
&lt;br /&gt;
==== 9 Chip String ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:2019_11_05.zip | 2019 November 5 ]]&lt;br /&gt;
* Some of the aluminium traces on the flex cable broke by the tail of the cable (near the ZIF stiffener). [[Media:Tail_modifications.png | Current design and possible modifications]] shows the current design and two possible modifications. It has been decided that new designs will use the &#039;&#039;&#039;design 1 modification&#039;&#039;&#039; and &#039;&#039;&#039;longer ZIF-stiffener&#039;&#039;&#039; (30 mm long).&lt;br /&gt;
&lt;br /&gt;
=== Production Test Box (PTB) ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:PTB-v1.0_schematic.pdf | PTB-v1.0 Schematic]]&lt;br /&gt;
* [[:Media:PTB-v1.0_samtec.zip | PTB-v1.0 FPGA Connections]]&lt;br /&gt;
* [[:Media:PTB-v1.0_yamaichi.zip | PTB-v1.0 Yamaichi Connections]]&lt;br /&gt;
&lt;br /&gt;
=== FPGA Mezzanine Card (FMC) ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:FMC-v1.0_schematic.pdf | FMC-v1.0 Schematic]]&lt;br /&gt;
&lt;br /&gt;
=== mTower ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:mTower_schematic.pdf | mTower Schematic]]&lt;br /&gt;
&lt;br /&gt;
=== Cooling Laboratory Setup ===&lt;br /&gt;
&lt;br /&gt;
1x LAUDA Ultracool UC 4 is used for water cooling in the laboratory now ([https://www.lauda.de/pim/datasheet/LAUDA_UC4_E6004411_en_20211220_135424.pdf data sheet] and [https://cdn.accentuate.io/6800432890013/1624628180288/DMI-0210-01_UC_2-4__EN_.pdf?v=0 manual]).&lt;br /&gt;
&lt;br /&gt;
1x Digital flow switch with temperature sensor for the cold plate (flow rate 13,6 l/min) SMC PF3W520S-04-2T-R-X128 &lt;br /&gt;
&lt;br /&gt;
1x Digital flow switch with temperature sensor for the tracking layers (flow rate 3,2 l/min) SMC PF3W504S-03-2T-R-X128 &lt;br /&gt;
&lt;br /&gt;
2x Digital flow monitor (SMC PFG310-SV)&lt;br /&gt;
&lt;br /&gt;
4x Meas Heavy Industrial Pressure Transmitter (M5131-70010X-004BC)&lt;br /&gt;
&lt;br /&gt;
3x Axial fans 4-wire 12V&lt;br /&gt;
&lt;br /&gt;
1x I/O Module Moxa ioLogik E1212 (8x digital inputs, 8x digital inputs/outputs)&lt;br /&gt;
&lt;br /&gt;
1x I/O Module Moxa ioLogik E1240 (8x analog inputs)&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
* [[:Media:PCT_lab_setup.pdf | Schematic of the pCT lab setup]]&lt;/div&gt;</summary>
		<author><name>Xej010</name></author>
	</entry>
	<entry>
		<id>https://pct.wiki.uib.no/index.php?title=Hardware_Documentation_and_Howto%27s&amp;diff=987</id>
		<title>Hardware Documentation and Howto&#039;s</title>
		<link rel="alternate" type="text/html" href="https://pct.wiki.uib.no/index.php?title=Hardware_Documentation_and_Howto%27s&amp;diff=987"/>
		<updated>2022-04-13T12:49:05Z</updated>

		<summary type="html">&lt;p&gt;Xej010: /* Cooling Laboratory Setup */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;[[Main Page]] -&amp;gt; [[Hardware Documentation and Howto&#039;s]]&lt;br /&gt;
&lt;br /&gt;
== Getting Started ==&lt;br /&gt;
&lt;br /&gt;
* [[Getting Started VCU118|VCU118]]&lt;br /&gt;
* [[Getting Started PTB|PTB]]&lt;br /&gt;
&lt;br /&gt;
== Documentation ==&lt;br /&gt;
&lt;br /&gt;
=== pRU ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Clock_network.png | pRU Clock Network]]&lt;br /&gt;
* [[:Media:PRU Address Map.pdf | pRU Address Map]]&lt;br /&gt;
* [[:Media:PRU Ethernet Configurations.pdf | DCS and Data Offload Ethernet Configurations]]&lt;br /&gt;
* [[:Media:PDTP.pdf | pCT Data Transfer Protocol]]&lt;br /&gt;
* [[:Media:Data format v0.2.pdf | pRU Data Format]]&lt;br /&gt;
* [[:Media:FpgaCalc.ods | FPGA and ALPIDE radiation calculations]]&lt;br /&gt;
* [[:Media:Control Interface.pdf | pRU Control Interface]] [Deprecated, only in use on PTB. Replaced with IPBus on VCU118 + all other boards in the future.]&lt;br /&gt;
&lt;br /&gt;
==== pRU Registers and Bus System ====&lt;br /&gt;
[[File:Top level firmware.png|500px]][[File:Bus tree.png|500px]]&lt;br /&gt;
&lt;br /&gt;
The pRU bus system is connecting the various modules on the FPGA to a common master, the Microblaze Subsystem.&lt;br /&gt;
Each of the modules is associated with a given BASE-ADDRESS specified in the [[:Media:Control Interface.pdf | pRU Control Interface Document]].&lt;br /&gt;
Note that several instances do exist for certain modules. E.g. there are one alpide_data instance for each ALPIDE chip connected to the pRU.&lt;br /&gt;
To communicate with a specific instance one needs to add an offset of 0x1000 times the instance number to the module base address.&lt;br /&gt;
&lt;br /&gt;
E.g. if you want to communicate with the &lt;br /&gt;
&lt;br /&gt;
* 1st instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt;&lt;br /&gt;
&lt;br /&gt;
* 2nd instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt; + (0x1000 * (2-1))&lt;br /&gt;
&lt;br /&gt;
* 16th instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt; + (0x1000 * (16-1))&lt;br /&gt;
&lt;br /&gt;
===== Module Registers =====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Global_regs.pdf | global_regs]]&lt;br /&gt;
* [[:Media:Trigger_manager.pdf | trigger_manager]]&lt;br /&gt;
* [[:Media:Offload.pdf | offload]]&lt;br /&gt;
* [[:Media:Alpide_control.pdf | alpide_control]]&lt;br /&gt;
* [[:Media:Alpide_data.pdf | alpide_data]]&lt;br /&gt;
&lt;br /&gt;
==== PTB-specific Module Registers ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Power_control.pdf | power_control]]&lt;br /&gt;
* [[:Media:Ptb_regs.pdf | ptb_regs]]&lt;br /&gt;
&lt;br /&gt;
=== Transition Card (TC) ===&lt;br /&gt;
&lt;br /&gt;
*  [[Media:TC-v1.0_schematic.pdf | TC-v1.0 Schematic]]&lt;br /&gt;
&lt;br /&gt;
=== ALPIDE Chip ===&lt;br /&gt;
&lt;br /&gt;
* [[Media:Alpide manual ver3.pdf | ALPIDE Manual v0.3]]&lt;br /&gt;
&lt;br /&gt;
=== ALPIDE Bonding and Mounting ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Report_Feb_2019.pdf | 9-chip String Simulation - and proposed 9-chip string redesign - 2019 Feb ]]&lt;br /&gt;
&lt;br /&gt;
==== Chip Cable ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:2020_01_08.zip | 2020 January 8 ]]&lt;br /&gt;
* [[:Media:2019_05_16.zip | 2019 May 16 (ULTM)]]&lt;br /&gt;
&lt;br /&gt;
==== 9 Chip String ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:2019_11_05.zip | 2019 November 5 ]]&lt;br /&gt;
* Some of the aluminium traces on the flex cable broke by the tail of the cable (near the ZIF stiffener). [[Media:Tail_modifications.png | Current design and possible modifications]] shows the current design and two possible modifications. It has been decided that new designs will use the &#039;&#039;&#039;design 1 modification&#039;&#039;&#039; and &#039;&#039;&#039;longer ZIF-stiffener&#039;&#039;&#039; (30 mm long).&lt;br /&gt;
&lt;br /&gt;
=== Production Test Box (PTB) ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:PTB-v1.0_schematic.pdf | PTB-v1.0 Schematic]]&lt;br /&gt;
* [[:Media:PTB-v1.0_samtec.zip | PTB-v1.0 FPGA Connections]]&lt;br /&gt;
* [[:Media:PTB-v1.0_yamaichi.zip | PTB-v1.0 Yamaichi Connections]]&lt;br /&gt;
&lt;br /&gt;
=== FPGA Mezzanine Card (FMC) ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:FMC-v1.0_schematic.pdf | FMC-v1.0 Schematic]]&lt;br /&gt;
&lt;br /&gt;
=== mTower ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:mTower_schematic.pdf | mTower Schematic]]&lt;br /&gt;
&lt;br /&gt;
=== Cooling Laboratory Setup ===&lt;br /&gt;
&lt;br /&gt;
1x LAUDA Ultracool UC 4 is used for water cooling in the laboratory now ([https://www.lauda.de/pim/datasheet/LAUDA_UC4_E6004411_en_20211220_135424.pdf data sheet] and [https://cdn.accentuate.io/6800432890013/1624628180288/DMI-0210-01_UC_2-4__EN_.pdf?v=0 manual]).&lt;br /&gt;
&lt;br /&gt;
1x Digital flow switch with temperature sensor for the cold plate (flow rate 13,6 l/min) SMC PF3W520S-04-2T-R-X128 &lt;br /&gt;
&lt;br /&gt;
1x Digital flow switch with temperature sensor for the tracking layers (flow rate 3,2 l/min) SMC PF3W504S-03-2T-R-X128 &lt;br /&gt;
&lt;br /&gt;
2x Digital flow monitor (SMC PFG310-SV)&lt;br /&gt;
&lt;br /&gt;
4x Meas Heavy Industrial Pressure Transmitter (M5131-70010X-004BC)&lt;br /&gt;
&lt;br /&gt;
3x Axial fans 4-wire 12V&lt;br /&gt;
&lt;br /&gt;
1x I/O Module Moxa ioLogik E1212 (8x digital inputs, 8x digital inputs/outputs)&lt;br /&gt;
&lt;br /&gt;
1x I/O Module Moxa ioLogik E1240 (8x analog inputs)&lt;/div&gt;</summary>
		<author><name>Xej010</name></author>
	</entry>
	<entry>
		<id>https://pct.wiki.uib.no/index.php?title=File:PCT_lab_setup.pdf&amp;diff=986</id>
		<title>File:PCT lab setup.pdf</title>
		<link rel="alternate" type="text/html" href="https://pct.wiki.uib.no/index.php?title=File:PCT_lab_setup.pdf&amp;diff=986"/>
		<updated>2022-04-13T12:41:22Z</updated>

		<summary type="html">&lt;p&gt;Xej010: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;&lt;/div&gt;</summary>
		<author><name>Xej010</name></author>
	</entry>
	<entry>
		<id>https://pct.wiki.uib.no/index.php?title=Hardware_Documentation_and_Howto%27s&amp;diff=985</id>
		<title>Hardware Documentation and Howto&#039;s</title>
		<link rel="alternate" type="text/html" href="https://pct.wiki.uib.no/index.php?title=Hardware_Documentation_and_Howto%27s&amp;diff=985"/>
		<updated>2022-04-13T12:40:25Z</updated>

		<summary type="html">&lt;p&gt;Xej010: /* Cooling Laboratory Setup */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;[[Main Page]] -&amp;gt; [[Hardware Documentation and Howto&#039;s]]&lt;br /&gt;
&lt;br /&gt;
== Getting Started ==&lt;br /&gt;
&lt;br /&gt;
* [[Getting Started VCU118|VCU118]]&lt;br /&gt;
* [[Getting Started PTB|PTB]]&lt;br /&gt;
&lt;br /&gt;
== Documentation ==&lt;br /&gt;
&lt;br /&gt;
=== pRU ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Clock_network.png | pRU Clock Network]]&lt;br /&gt;
* [[:Media:PRU Address Map.pdf | pRU Address Map]]&lt;br /&gt;
* [[:Media:PRU Ethernet Configurations.pdf | DCS and Data Offload Ethernet Configurations]]&lt;br /&gt;
* [[:Media:PDTP.pdf | pCT Data Transfer Protocol]]&lt;br /&gt;
* [[:Media:Data format v0.2.pdf | pRU Data Format]]&lt;br /&gt;
* [[:Media:FpgaCalc.ods | FPGA and ALPIDE radiation calculations]]&lt;br /&gt;
* [[:Media:Control Interface.pdf | pRU Control Interface]] [Deprecated, only in use on PTB. Replaced with IPBus on VCU118 + all other boards in the future.]&lt;br /&gt;
&lt;br /&gt;
==== pRU Registers and Bus System ====&lt;br /&gt;
[[File:Top level firmware.png|500px]][[File:Bus tree.png|500px]]&lt;br /&gt;
&lt;br /&gt;
The pRU bus system is connecting the various modules on the FPGA to a common master, the Microblaze Subsystem.&lt;br /&gt;
Each of the modules is associated with a given BASE-ADDRESS specified in the [[:Media:Control Interface.pdf | pRU Control Interface Document]].&lt;br /&gt;
Note that several instances do exist for certain modules. E.g. there are one alpide_data instance for each ALPIDE chip connected to the pRU.&lt;br /&gt;
To communicate with a specific instance one needs to add an offset of 0x1000 times the instance number to the module base address.&lt;br /&gt;
&lt;br /&gt;
E.g. if you want to communicate with the &lt;br /&gt;
&lt;br /&gt;
* 1st instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt;&lt;br /&gt;
&lt;br /&gt;
* 2nd instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt; + (0x1000 * (2-1))&lt;br /&gt;
&lt;br /&gt;
* 16th instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt; + (0x1000 * (16-1))&lt;br /&gt;
&lt;br /&gt;
===== Module Registers =====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Global_regs.pdf | global_regs]]&lt;br /&gt;
* [[:Media:Trigger_manager.pdf | trigger_manager]]&lt;br /&gt;
* [[:Media:Offload.pdf | offload]]&lt;br /&gt;
* [[:Media:Alpide_control.pdf | alpide_control]]&lt;br /&gt;
* [[:Media:Alpide_data.pdf | alpide_data]]&lt;br /&gt;
&lt;br /&gt;
==== PTB-specific Module Registers ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Power_control.pdf | power_control]]&lt;br /&gt;
* [[:Media:Ptb_regs.pdf | ptb_regs]]&lt;br /&gt;
&lt;br /&gt;
=== Transition Card (TC) ===&lt;br /&gt;
&lt;br /&gt;
*  [[Media:TC-v1.0_schematic.pdf | TC-v1.0 Schematic]]&lt;br /&gt;
&lt;br /&gt;
=== ALPIDE Chip ===&lt;br /&gt;
&lt;br /&gt;
* [[Media:Alpide manual ver3.pdf | ALPIDE Manual v0.3]]&lt;br /&gt;
&lt;br /&gt;
=== ALPIDE Bonding and Mounting ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Report_Feb_2019.pdf | 9-chip String Simulation - and proposed 9-chip string redesign - 2019 Feb ]]&lt;br /&gt;
&lt;br /&gt;
==== Chip Cable ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:2020_01_08.zip | 2020 January 8 ]]&lt;br /&gt;
* [[:Media:2019_05_16.zip | 2019 May 16 (ULTM)]]&lt;br /&gt;
&lt;br /&gt;
==== 9 Chip String ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:2019_11_05.zip | 2019 November 5 ]]&lt;br /&gt;
* Some of the aluminium traces on the flex cable broke by the tail of the cable (near the ZIF stiffener). [[Media:Tail_modifications.png | Current design and possible modifications]] shows the current design and two possible modifications. It has been decided that new designs will use the &#039;&#039;&#039;design 1 modification&#039;&#039;&#039; and &#039;&#039;&#039;longer ZIF-stiffener&#039;&#039;&#039; (30 mm long).&lt;br /&gt;
&lt;br /&gt;
=== Production Test Box (PTB) ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:PTB-v1.0_schematic.pdf | PTB-v1.0 Schematic]]&lt;br /&gt;
* [[:Media:PTB-v1.0_samtec.zip | PTB-v1.0 FPGA Connections]]&lt;br /&gt;
* [[:Media:PTB-v1.0_yamaichi.zip | PTB-v1.0 Yamaichi Connections]]&lt;br /&gt;
&lt;br /&gt;
=== FPGA Mezzanine Card (FMC) ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:FMC-v1.0_schematic.pdf | FMC-v1.0 Schematic]]&lt;br /&gt;
&lt;br /&gt;
=== mTower ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:mTower_schematic.pdf | mTower Schematic]]&lt;br /&gt;
&lt;br /&gt;
=== Cooling Laboratory Setup ===&lt;br /&gt;
&lt;br /&gt;
1x LAUDA Ultracool UC 4 is used for water cooling in the laboratory now ([https://www.lauda.de/pim/datasheet/LAUDA_UC4_E6004411_en_20211220_135424.pdf data sheet] and [https://cdn.accentuate.io/6800432890013/1624628180288/DMI-0210-01_UC_2-4__EN_.pdf?v=0 manual]).&lt;br /&gt;
&lt;br /&gt;
1x Digital flow switch with temperature sensor for the cold plate (flow rate 13,6 l/min) SMC PF3W520S-04-2T-R-X128 &lt;br /&gt;
&lt;br /&gt;
1x Digital flow switch with temperature sensor for the tracking layers (flow rate 3,2 l/min) SMC PF3W504S-03-2T-R-X128 &lt;br /&gt;
&lt;br /&gt;
2x Digital flow monitor (SMC PFG310-SV)&lt;br /&gt;
&lt;br /&gt;
4x Meas Heavy Industrial Pressure Transmitter (M5131-70010X-004BC)&lt;br /&gt;
&lt;br /&gt;
3x Axial fans 4-wire 12V&lt;/div&gt;</summary>
		<author><name>Xej010</name></author>
	</entry>
	<entry>
		<id>https://pct.wiki.uib.no/index.php?title=Hardware_Documentation_and_Howto%27s&amp;diff=982</id>
		<title>Hardware Documentation and Howto&#039;s</title>
		<link rel="alternate" type="text/html" href="https://pct.wiki.uib.no/index.php?title=Hardware_Documentation_and_Howto%27s&amp;diff=982"/>
		<updated>2022-01-25T14:04:54Z</updated>

		<summary type="html">&lt;p&gt;Xej010: /* Cooling Laboratory Setup */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;[[Main Page]] -&amp;gt; [[Hardware Documentation and Howto&#039;s]]&lt;br /&gt;
&lt;br /&gt;
== Getting Started ==&lt;br /&gt;
&lt;br /&gt;
* [[Getting Started VCU118|VCU118]]&lt;br /&gt;
* [[Getting Started PTB|PTB]]&lt;br /&gt;
&lt;br /&gt;
== Documentation ==&lt;br /&gt;
&lt;br /&gt;
=== pRU ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Clock_network.png | pRU Clock Network]]&lt;br /&gt;
* [[:Media:PRU Address Map.pdf | pRU Address Map]]&lt;br /&gt;
* [[:Media:PRU Ethernet Configurations.pdf | DCS and Data Offload Ethernet Configurations]]&lt;br /&gt;
* [[:Media:PDTP.pdf | pCT Data Transfer Protocol]]&lt;br /&gt;
* [[:Media:Data format v0.2.pdf | pRU Data Format]]&lt;br /&gt;
* [[:Media:FpgaCalc.ods | FPGA and ALPIDE radiation calculations]]&lt;br /&gt;
* [[:Media:Control Interface.pdf | pRU Control Interface]] [Deprecated, only in use on PTB. Replaced with IPBus on VCU118 + all other boards in the future.]&lt;br /&gt;
&lt;br /&gt;
==== pRU Registers and Bus System ====&lt;br /&gt;
[[File:Top level firmware.png|500px]][[File:Bus tree.png|500px]]&lt;br /&gt;
&lt;br /&gt;
The pRU bus system is connecting the various modules on the FPGA to a common master, the Microblaze Subsystem.&lt;br /&gt;
Each of the modules is associated with a given BASE-ADDRESS specified in the [[:Media:Control Interface.pdf | pRU Control Interface Document]].&lt;br /&gt;
Note that several instances do exist for certain modules. E.g. there are one alpide_data instance for each ALPIDE chip connected to the pRU.&lt;br /&gt;
To communicate with a specific instance one needs to add an offset of 0x1000 times the instance number to the module base address.&lt;br /&gt;
&lt;br /&gt;
E.g. if you want to communicate with the &lt;br /&gt;
&lt;br /&gt;
* 1st instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt;&lt;br /&gt;
&lt;br /&gt;
* 2nd instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt; + (0x1000 * (2-1))&lt;br /&gt;
&lt;br /&gt;
* 16th instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt; + (0x1000 * (16-1))&lt;br /&gt;
&lt;br /&gt;
===== Module Registers =====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Global_regs.pdf | global_regs]]&lt;br /&gt;
* [[:Media:Trigger_manager.pdf | trigger_manager]]&lt;br /&gt;
* [[:Media:Offload.pdf | offload]]&lt;br /&gt;
* [[:Media:Alpide_control.pdf | alpide_control]]&lt;br /&gt;
* [[:Media:Alpide_data.pdf | alpide_data]]&lt;br /&gt;
&lt;br /&gt;
==== PTB-specific Module Registers ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Power_control.pdf | power_control]]&lt;br /&gt;
* [[:Media:Ptb_regs.pdf | ptb_regs]]&lt;br /&gt;
&lt;br /&gt;
=== Transition Card (TC) ===&lt;br /&gt;
&lt;br /&gt;
*  [[Media:TC-v1.0_schematic.pdf | TC-v1.0 Schematic]]&lt;br /&gt;
&lt;br /&gt;
=== ALPIDE Chip ===&lt;br /&gt;
&lt;br /&gt;
* [[Media:Alpide manual ver3.pdf | ALPIDE Manual v0.3]]&lt;br /&gt;
&lt;br /&gt;
=== ALPIDE Bonding and Mounting ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Report_Feb_2019.pdf | 9-chip String Simulation - and proposed 9-chip string redesign - 2019 Feb ]]&lt;br /&gt;
&lt;br /&gt;
==== Chip Cable ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:2020_01_08.zip | 2020 January 8 ]]&lt;br /&gt;
* [[:Media:2019_05_16.zip | 2019 May 16 (ULTM)]]&lt;br /&gt;
&lt;br /&gt;
==== 9 Chip String ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:2019_11_05.zip | 2019 November 5 ]]&lt;br /&gt;
* Some of the aluminium traces on the flex cable broke by the tail of the cable (near the ZIF stiffener). [[Media:Tail_modifications.png | Current design and possible modifications]] shows the current design and two possible modifications. It has been decided that new designs will use the &#039;&#039;&#039;design 1 modification&#039;&#039;&#039; and &#039;&#039;&#039;longer ZIF-stiffener&#039;&#039;&#039; (30 mm long).&lt;br /&gt;
&lt;br /&gt;
=== Production Test Box (PTB) ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:PTB-v1.0_schematic.pdf | PTB-v1.0 Schematic]]&lt;br /&gt;
* [[:Media:PTB-v1.0_samtec.zip | PTB-v1.0 FPGA Connections]]&lt;br /&gt;
* [[:Media:PTB-v1.0_yamaichi.zip | PTB-v1.0 Yamaichi Connections]]&lt;br /&gt;
&lt;br /&gt;
=== FPGA Mezzanine Card (FMC) ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:FMC-v1.0_schematic.pdf | FMC-v1.0 Schematic]]&lt;br /&gt;
&lt;br /&gt;
=== mTower ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:mTower_schematic.pdf | mTower Schematic]]&lt;br /&gt;
&lt;br /&gt;
=== Cooling Laboratory Setup ===&lt;br /&gt;
&lt;br /&gt;
1x LAUDA Ultracool UC 4 is used for water cooling in the laboratory now ([https://www.lauda.de/pim/datasheet/LAUDA_UC4_E6004411_en_20211220_135424.pdf data sheet] and [https://cdn.accentuate.io/6800432890013/1624628180288/DMI-0210-01_UC_2-4__EN_.pdf?v=0 manual]).&lt;br /&gt;
&lt;br /&gt;
1x Digital flow switch with temperature sensor for the cold plate (flow rate 13,6 l/min) SMC PF3W520S-04-2T-R-X128 &lt;br /&gt;
&lt;br /&gt;
1x Digital flow switch with temperature sensor for the tracking layers (flow rate 3,2 l/min) SMC PF3W504S-03-2T-R-X128 &lt;br /&gt;
&lt;br /&gt;
2x Digital flow monitor (SMC PFG310-SV)&lt;br /&gt;
&lt;br /&gt;
4x Meas Heavy Industrial Pressure Transmitter (M5131-70010X-004BC)&lt;br /&gt;
&lt;br /&gt;
3x Axial fans 4-wire 12V&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
Only for testing &lt;br /&gt;
&lt;br /&gt;
?x Temperature sensors&lt;br /&gt;
&lt;br /&gt;
2x Heating pads calorimeter&lt;br /&gt;
&lt;br /&gt;
1x Heating pads tracking layer&lt;/div&gt;</summary>
		<author><name>Xej010</name></author>
	</entry>
	<entry>
		<id>https://pct.wiki.uib.no/index.php?title=Hardware_Documentation_and_Howto%27s&amp;diff=962</id>
		<title>Hardware Documentation and Howto&#039;s</title>
		<link rel="alternate" type="text/html" href="https://pct.wiki.uib.no/index.php?title=Hardware_Documentation_and_Howto%27s&amp;diff=962"/>
		<updated>2022-01-19T14:04:52Z</updated>

		<summary type="html">&lt;p&gt;Xej010: /* Cooling Laboratory Setup */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;[[Main Page]] -&amp;gt; [[Hardware Documentation and Howto&#039;s]]&lt;br /&gt;
&lt;br /&gt;
== Getting Started ==&lt;br /&gt;
&lt;br /&gt;
* [[Getting Started VCU118|VCU118]]&lt;br /&gt;
* [[Getting Started PTB|PTB]]&lt;br /&gt;
&lt;br /&gt;
== Documentation ==&lt;br /&gt;
&lt;br /&gt;
=== pRU ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Clock_network.png | pRU Clock Network]]&lt;br /&gt;
* [[:Media:PRU Address Map.pdf | pRU Address Map]]&lt;br /&gt;
* [[:Media:PRU Ethernet Configurations.pdf | DCS and Data Offload Ethernet Configurations]]&lt;br /&gt;
* [[:Media:PDTP.pdf | pCT Data Transfer Protocol]]&lt;br /&gt;
* [[:Media:Data format v0.2.pdf | pRU Data Format]]&lt;br /&gt;
* [[:Media:FpgaCalc.ods | FPGA and ALPIDE radiation calculations]]&lt;br /&gt;
* [[:Media:Control Interface.pdf | pRU Control Interface]] [Deprecated, only in use on PTB. Replaced with IPBus on VCU118 + all other boards in the future.]&lt;br /&gt;
&lt;br /&gt;
==== pRU Registers and Bus System ====&lt;br /&gt;
[[File:Top level firmware.png|500px]][[File:Bus tree.png|500px]]&lt;br /&gt;
&lt;br /&gt;
The pRU bus system is connecting the various modules on the FPGA to a common master, the Microblaze Subsystem.&lt;br /&gt;
Each of the modules is associated with a given BASE-ADDRESS specified in the [[:Media:Control Interface.pdf | pRU Control Interface Document]].&lt;br /&gt;
Note that several instances do exist for certain modules. E.g. there are one alpide_data instance for each ALPIDE chip connected to the pRU.&lt;br /&gt;
To communicate with a specific instance one needs to add an offset of 0x1000 times the instance number to the module base address.&lt;br /&gt;
&lt;br /&gt;
E.g. if you want to communicate with the &lt;br /&gt;
&lt;br /&gt;
* 1st instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt;&lt;br /&gt;
&lt;br /&gt;
* 2nd instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt; + (0x1000 * (2-1))&lt;br /&gt;
&lt;br /&gt;
* 16th instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt; + (0x1000 * (16-1))&lt;br /&gt;
&lt;br /&gt;
===== Module Registers =====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Global_regs.pdf | global_regs]]&lt;br /&gt;
* [[:Media:Trigger_manager.pdf | trigger_manager]]&lt;br /&gt;
* [[:Media:Offload.pdf | offload]]&lt;br /&gt;
* [[:Media:Alpide_control.pdf | alpide_control]]&lt;br /&gt;
* [[:Media:Alpide_data.pdf | alpide_data]]&lt;br /&gt;
&lt;br /&gt;
==== PTB-specific Module Registers ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Power_control.pdf | power_control]]&lt;br /&gt;
* [[:Media:Ptb_regs.pdf | ptb_regs]]&lt;br /&gt;
&lt;br /&gt;
=== Transition Card (TC) ===&lt;br /&gt;
&lt;br /&gt;
*  [[Media:TC-v1.0_schematic.pdf | TC-v1.0 Schematic]]&lt;br /&gt;
&lt;br /&gt;
=== ALPIDE Chip ===&lt;br /&gt;
&lt;br /&gt;
* [[Media:Alpide manual ver3.pdf | ALPIDE Manual v0.3]]&lt;br /&gt;
&lt;br /&gt;
=== ALPIDE Bonding and Mounting ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Report_Feb_2019.pdf | 9-chip String Simulation - and proposed 9-chip string redesign - 2019 Feb ]]&lt;br /&gt;
&lt;br /&gt;
==== Chip Cable ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:2020_01_08.zip | 2020 January 8 ]]&lt;br /&gt;
* [[:Media:2019_05_16.zip | 2019 May 16 (ULTM)]]&lt;br /&gt;
&lt;br /&gt;
==== 9 Chip String ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:2019_11_05.zip | 2019 November 5 ]]&lt;br /&gt;
* Some of the aluminium traces on the flex cable broke by the tail of the cable (near the ZIF stiffener). [[Media:Tail_modifications.png | Current design and possible modifications]] shows the current design and two possible modifications. It has been decided that new designs will use the &#039;&#039;&#039;design 1 modification&#039;&#039;&#039; and &#039;&#039;&#039;longer ZIF-stiffener&#039;&#039;&#039; (30 mm long).&lt;br /&gt;
&lt;br /&gt;
=== Production Test Box (PTB) ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:PTB-v1.0_schematic.pdf | PTB-v1.0 Schematic]]&lt;br /&gt;
* [[:Media:PTB-v1.0_samtec.zip | PTB-v1.0 FPGA Connections]]&lt;br /&gt;
* [[:Media:PTB-v1.0_yamaichi.zip | PTB-v1.0 Yamaichi Connections]]&lt;br /&gt;
&lt;br /&gt;
=== FPGA Mezzanine Card (FMC) ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:FMC-v1.0_schematic.pdf | FMC-v1.0 Schematic]]&lt;br /&gt;
&lt;br /&gt;
=== mTower ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:mTower_schematic.pdf | mTower Schematic]]&lt;br /&gt;
&lt;br /&gt;
=== Cooling Laboratory Setup ===&lt;br /&gt;
&lt;br /&gt;
1x LAUDA Ultracool UC 4 is used for water cooling in the laboratory now ([https://www.lauda.de/pim/datasheet/LAUDA_UC4_E6004411_en_20211220_135424.pdf data sheet] and [https://cdn.accentuate.io/6800432890013/1624628180288/DMI-0210-01_UC_2-4__EN_.pdf?v=0 manual]).&lt;br /&gt;
&lt;br /&gt;
2x Digital flow switch (SMC PF3W520S-04-2T-R-X128) &lt;br /&gt;
&lt;br /&gt;
2x Digital flow monitor (SMC PFG310-SV)&lt;br /&gt;
&lt;br /&gt;
4x Meas Heavy Industrial Pressure Transmitter (M5131-70010X-004BC)&lt;br /&gt;
&lt;br /&gt;
3x Axial fans 4-wire 12V&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
Only for testing &lt;br /&gt;
&lt;br /&gt;
?x Temperature sensors&lt;br /&gt;
&lt;br /&gt;
2x Heating pads calorimeter&lt;br /&gt;
&lt;br /&gt;
1x Heating pads tracking layer&lt;/div&gt;</summary>
		<author><name>Xej010</name></author>
	</entry>
	<entry>
		<id>https://pct.wiki.uib.no/index.php?title=Commissioning&amp;diff=961</id>
		<title>Commissioning</title>
		<link rel="alternate" type="text/html" href="https://pct.wiki.uib.no/index.php?title=Commissioning&amp;diff=961"/>
		<updated>2022-01-11T13:22:44Z</updated>

		<summary type="html">&lt;p&gt;Xej010: /* Beam test 2021 */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;[[Main Page]] -&amp;gt; [[Commissioning]]&lt;br /&gt;
&lt;br /&gt;
= Beam test 2021 =&lt;br /&gt;
Since the beam test has been coordinated by the FoCal project, which uses a similar setup in the pixel layers as pCT, all information regarding the test can be found here [https://twiki.cern.ch/twiki/bin/view/ALICE/FocalTestBeam2021 FoCal Wiki].&lt;br /&gt;
&lt;br /&gt;
== Dates ==&lt;br /&gt;
22 September - 6 October 2021 @ SPS&lt;br /&gt;
&lt;br /&gt;
== Objectives ==&lt;br /&gt;
&lt;br /&gt;
== Hardware ==&lt;br /&gt;
&lt;br /&gt;
== Software ==&lt;br /&gt;
O2 readout tools going to be used to get data from CRU, need the decoder/parser process for the RDH format&lt;br /&gt;
&lt;br /&gt;
Some ALICE tools&lt;br /&gt;
* https://github.com/JianLIUhep/QCUtils&lt;br /&gt;
* https://gitlab.cern.ch/alice-its-wp10-firmware/rawdata-parser&lt;br /&gt;
&lt;br /&gt;
== Planning ==&lt;br /&gt;
The current checklist can be found and edited here: [https://universityofbergen-my.sharepoint.com/:x:/g/personal/viljar_eikeland_uib_no/EWcbIUUzNhZJuWWOg1HhRVEBo2HxSJ37qlY-3kWdB8ZJ5Q?e=kq7bel Checklist SPS]&lt;br /&gt;
&lt;br /&gt;
The current global planning can be found and edited here: [https://universityofbergen-my.sharepoint.com/:x:/g/personal/viljar_eikeland_uib_no/EftvnGEYTd5Mr5w7mGY6SuQBn5BEBtPJI_7_aH78LVPOHg?e=H9qscW Global planning SPS]&lt;/div&gt;</summary>
		<author><name>Xej010</name></author>
	</entry>
	<entry>
		<id>https://pct.wiki.uib.no/index.php?title=Hardware_Documentation_and_Howto%27s&amp;diff=960</id>
		<title>Hardware Documentation and Howto&#039;s</title>
		<link rel="alternate" type="text/html" href="https://pct.wiki.uib.no/index.php?title=Hardware_Documentation_and_Howto%27s&amp;diff=960"/>
		<updated>2022-01-10T14:18:22Z</updated>

		<summary type="html">&lt;p&gt;Xej010: /* 9 Chip String */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;[[Main Page]] -&amp;gt; [[Hardware Documentation and Howto&#039;s]]&lt;br /&gt;
&lt;br /&gt;
== Getting Started ==&lt;br /&gt;
&lt;br /&gt;
* [[Getting Started VCU118|VCU118]]&lt;br /&gt;
* [[Getting Started PTB|PTB]]&lt;br /&gt;
&lt;br /&gt;
== Documentation ==&lt;br /&gt;
&lt;br /&gt;
=== pRU ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Clock_network.png | pRU Clock Network]]&lt;br /&gt;
* [[:Media:PRU Address Map.pdf | pRU Address Map]]&lt;br /&gt;
* [[:Media:PRU Ethernet Configurations.pdf | DCS and Data Offload Ethernet Configurations]]&lt;br /&gt;
* [[:Media:PDTP.pdf | pCT Data Transfer Protocol]]&lt;br /&gt;
* [[:Media:Data format v0.2.pdf | pRU Data Format]]&lt;br /&gt;
* [[:Media:FpgaCalc.ods | FPGA and ALPIDE radiation calculations]]&lt;br /&gt;
* [[:Media:Control Interface.pdf | pRU Control Interface]] [Deprecated, only in use on PTB. Replaced with IPBus on VCU118 + all other boards in the future.]&lt;br /&gt;
&lt;br /&gt;
==== pRU Registers and Bus System ====&lt;br /&gt;
[[File:Top level firmware.png|500px]][[File:Bus tree.png|500px]]&lt;br /&gt;
&lt;br /&gt;
The pRU bus system is connecting the various modules on the FPGA to a common master, the Microblaze Subsystem.&lt;br /&gt;
Each of the modules is associated with a given BASE-ADDRESS specified in the [[:Media:Control Interface.pdf | pRU Control Interface Document]].&lt;br /&gt;
Note that several instances do exist for certain modules. E.g. there are one alpide_data instance for each ALPIDE chip connected to the pRU.&lt;br /&gt;
To communicate with a specific instance one needs to add an offset of 0x1000 times the instance number to the module base address.&lt;br /&gt;
&lt;br /&gt;
E.g. if you want to communicate with the &lt;br /&gt;
&lt;br /&gt;
* 1st instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt;&lt;br /&gt;
&lt;br /&gt;
* 2nd instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt; + (0x1000 * (2-1))&lt;br /&gt;
&lt;br /&gt;
* 16th instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt; + (0x1000 * (16-1))&lt;br /&gt;
&lt;br /&gt;
===== Module Registers =====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Global_regs.pdf | global_regs]]&lt;br /&gt;
* [[:Media:Trigger_manager.pdf | trigger_manager]]&lt;br /&gt;
* [[:Media:Offload.pdf | offload]]&lt;br /&gt;
* [[:Media:Alpide_control.pdf | alpide_control]]&lt;br /&gt;
* [[:Media:Alpide_data.pdf | alpide_data]]&lt;br /&gt;
&lt;br /&gt;
==== PTB-specific Module Registers ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Power_control.pdf | power_control]]&lt;br /&gt;
* [[:Media:Ptb_regs.pdf | ptb_regs]]&lt;br /&gt;
&lt;br /&gt;
=== Transition Card (TC) ===&lt;br /&gt;
&lt;br /&gt;
*  [[Media:TC-v1.0_schematic.pdf | TC-v1.0 Schematic]]&lt;br /&gt;
&lt;br /&gt;
=== ALPIDE Chip ===&lt;br /&gt;
&lt;br /&gt;
* [[Media:Alpide manual ver3.pdf | ALPIDE Manual v0.3]]&lt;br /&gt;
&lt;br /&gt;
=== ALPIDE Bonding and Mounting ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Report_Feb_2019.pdf | 9-chip String Simulation - and proposed 9-chip string redesign - 2019 Feb ]]&lt;br /&gt;
&lt;br /&gt;
==== Chip Cable ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:2020_01_08.zip | 2020 January 8 ]]&lt;br /&gt;
* [[:Media:2019_05_16.zip | 2019 May 16 (ULTM)]]&lt;br /&gt;
&lt;br /&gt;
==== 9 Chip String ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:2019_11_05.zip | 2019 November 5 ]]&lt;br /&gt;
* Some of the aluminium traces on the flex cable broke by the tail of the cable (near the ZIF stiffener). [[Media:Tail_modifications.png | Current design and possible modifications]] shows the current design and two possible modifications. It has been decided that new designs will use the &#039;&#039;&#039;design 1 modification&#039;&#039;&#039; and &#039;&#039;&#039;longer ZIF-stiffener&#039;&#039;&#039; (30 mm long).&lt;br /&gt;
&lt;br /&gt;
=== Production Test Box (PTB) ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:PTB-v1.0_schematic.pdf | PTB-v1.0 Schematic]]&lt;br /&gt;
* [[:Media:PTB-v1.0_samtec.zip | PTB-v1.0 FPGA Connections]]&lt;br /&gt;
* [[:Media:PTB-v1.0_yamaichi.zip | PTB-v1.0 Yamaichi Connections]]&lt;br /&gt;
&lt;br /&gt;
=== FPGA Mezzanine Card (FMC) ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:FMC-v1.0_schematic.pdf | FMC-v1.0 Schematic]]&lt;br /&gt;
&lt;br /&gt;
=== mTower ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:mTower_schematic.pdf | mTower Schematic]]&lt;br /&gt;
&lt;br /&gt;
=== Cooling Laboratory Setup ===&lt;br /&gt;
&lt;br /&gt;
LAUDA Ultracool UC 4 is used for water cooling in the laboratory now ([https://www.lauda.de/pim/datasheet/LAUDA_UC4_E6004411_en_20211220_135424.pdf data sheet] and [https://cdn.accentuate.io/6800432890013/1624628180288/DMI-0210-01_UC_2-4__EN_.pdf?v=0 manual]).&lt;/div&gt;</summary>
		<author><name>Xej010</name></author>
	</entry>
	<entry>
		<id>https://pct.wiki.uib.no/index.php?title=Hardware_Documentation_and_Howto%27s&amp;diff=959</id>
		<title>Hardware Documentation and Howto&#039;s</title>
		<link rel="alternate" type="text/html" href="https://pct.wiki.uib.no/index.php?title=Hardware_Documentation_and_Howto%27s&amp;diff=959"/>
		<updated>2022-01-10T14:03:29Z</updated>

		<summary type="html">&lt;p&gt;Xej010: /* 9 Chip String */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;[[Main Page]] -&amp;gt; [[Hardware Documentation and Howto&#039;s]]&lt;br /&gt;
&lt;br /&gt;
== Getting Started ==&lt;br /&gt;
&lt;br /&gt;
* [[Getting Started VCU118|VCU118]]&lt;br /&gt;
* [[Getting Started PTB|PTB]]&lt;br /&gt;
&lt;br /&gt;
== Documentation ==&lt;br /&gt;
&lt;br /&gt;
=== pRU ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Clock_network.png | pRU Clock Network]]&lt;br /&gt;
* [[:Media:PRU Address Map.pdf | pRU Address Map]]&lt;br /&gt;
* [[:Media:PRU Ethernet Configurations.pdf | DCS and Data Offload Ethernet Configurations]]&lt;br /&gt;
* [[:Media:PDTP.pdf | pCT Data Transfer Protocol]]&lt;br /&gt;
* [[:Media:Data format v0.2.pdf | pRU Data Format]]&lt;br /&gt;
* [[:Media:FpgaCalc.ods | FPGA and ALPIDE radiation calculations]]&lt;br /&gt;
* [[:Media:Control Interface.pdf | pRU Control Interface]] [Deprecated, only in use on PTB. Replaced with IPBus on VCU118 + all other boards in the future.]&lt;br /&gt;
&lt;br /&gt;
==== pRU Registers and Bus System ====&lt;br /&gt;
[[File:Top level firmware.png|500px]][[File:Bus tree.png|500px]]&lt;br /&gt;
&lt;br /&gt;
The pRU bus system is connecting the various modules on the FPGA to a common master, the Microblaze Subsystem.&lt;br /&gt;
Each of the modules is associated with a given BASE-ADDRESS specified in the [[:Media:Control Interface.pdf | pRU Control Interface Document]].&lt;br /&gt;
Note that several instances do exist for certain modules. E.g. there are one alpide_data instance for each ALPIDE chip connected to the pRU.&lt;br /&gt;
To communicate with a specific instance one needs to add an offset of 0x1000 times the instance number to the module base address.&lt;br /&gt;
&lt;br /&gt;
E.g. if you want to communicate with the &lt;br /&gt;
&lt;br /&gt;
* 1st instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt;&lt;br /&gt;
&lt;br /&gt;
* 2nd instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt; + (0x1000 * (2-1))&lt;br /&gt;
&lt;br /&gt;
* 16th instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt; + (0x1000 * (16-1))&lt;br /&gt;
&lt;br /&gt;
===== Module Registers =====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Global_regs.pdf | global_regs]]&lt;br /&gt;
* [[:Media:Trigger_manager.pdf | trigger_manager]]&lt;br /&gt;
* [[:Media:Offload.pdf | offload]]&lt;br /&gt;
* [[:Media:Alpide_control.pdf | alpide_control]]&lt;br /&gt;
* [[:Media:Alpide_data.pdf | alpide_data]]&lt;br /&gt;
&lt;br /&gt;
==== PTB-specific Module Registers ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Power_control.pdf | power_control]]&lt;br /&gt;
* [[:Media:Ptb_regs.pdf | ptb_regs]]&lt;br /&gt;
&lt;br /&gt;
=== Transition Card (TC) ===&lt;br /&gt;
&lt;br /&gt;
*  [[Media:TC-v1.0_schematic.pdf | TC-v1.0 Schematic]]&lt;br /&gt;
&lt;br /&gt;
=== ALPIDE Chip ===&lt;br /&gt;
&lt;br /&gt;
* [[Media:Alpide manual ver3.pdf | ALPIDE Manual v0.3]]&lt;br /&gt;
&lt;br /&gt;
=== ALPIDE Bonding and Mounting ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Report_Feb_2019.pdf | 9-chip String Simulation - and proposed 9-chip string redesign - 2019 Feb ]]&lt;br /&gt;
&lt;br /&gt;
==== Chip Cable ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:2020_01_08.zip | 2020 January 8 ]]&lt;br /&gt;
* [[:Media:2019_05_16.zip | 2019 May 16 (ULTM)]]&lt;br /&gt;
&lt;br /&gt;
==== 9 Chip String ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:2019_11_05.zip | 2019 November 5 ]]&lt;br /&gt;
* Some of the aluminium traces on the flex cable broke by the tail of the cable (near the ZIF stiffener). [[Media:Tail_modifications.png | Current design and possible modifications]] shows the current design and two possible modifications. It has been decided that new designs will use the design 1 modification and longer ZIF-stiffener (30 mm long).&lt;br /&gt;
&lt;br /&gt;
=== Production Test Box (PTB) ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:PTB-v1.0_schematic.pdf | PTB-v1.0 Schematic]]&lt;br /&gt;
* [[:Media:PTB-v1.0_samtec.zip | PTB-v1.0 FPGA Connections]]&lt;br /&gt;
* [[:Media:PTB-v1.0_yamaichi.zip | PTB-v1.0 Yamaichi Connections]]&lt;br /&gt;
&lt;br /&gt;
=== FPGA Mezzanine Card (FMC) ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:FMC-v1.0_schematic.pdf | FMC-v1.0 Schematic]]&lt;br /&gt;
&lt;br /&gt;
=== mTower ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:mTower_schematic.pdf | mTower Schematic]]&lt;br /&gt;
&lt;br /&gt;
=== Cooling Laboratory Setup ===&lt;br /&gt;
&lt;br /&gt;
LAUDA Ultracool UC 4 is used for water cooling in the laboratory now ([https://www.lauda.de/pim/datasheet/LAUDA_UC4_E6004411_en_20211220_135424.pdf data sheet] and [https://cdn.accentuate.io/6800432890013/1624628180288/DMI-0210-01_UC_2-4__EN_.pdf?v=0 manual]).&lt;/div&gt;</summary>
		<author><name>Xej010</name></author>
	</entry>
	<entry>
		<id>https://pct.wiki.uib.no/index.php?title=Hardware_Documentation_and_Howto%27s&amp;diff=958</id>
		<title>Hardware Documentation and Howto&#039;s</title>
		<link rel="alternate" type="text/html" href="https://pct.wiki.uib.no/index.php?title=Hardware_Documentation_and_Howto%27s&amp;diff=958"/>
		<updated>2022-01-10T14:02:26Z</updated>

		<summary type="html">&lt;p&gt;Xej010: /* 9 Chip String */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;[[Main Page]] -&amp;gt; [[Hardware Documentation and Howto&#039;s]]&lt;br /&gt;
&lt;br /&gt;
== Getting Started ==&lt;br /&gt;
&lt;br /&gt;
* [[Getting Started VCU118|VCU118]]&lt;br /&gt;
* [[Getting Started PTB|PTB]]&lt;br /&gt;
&lt;br /&gt;
== Documentation ==&lt;br /&gt;
&lt;br /&gt;
=== pRU ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Clock_network.png | pRU Clock Network]]&lt;br /&gt;
* [[:Media:PRU Address Map.pdf | pRU Address Map]]&lt;br /&gt;
* [[:Media:PRU Ethernet Configurations.pdf | DCS and Data Offload Ethernet Configurations]]&lt;br /&gt;
* [[:Media:PDTP.pdf | pCT Data Transfer Protocol]]&lt;br /&gt;
* [[:Media:Data format v0.2.pdf | pRU Data Format]]&lt;br /&gt;
* [[:Media:FpgaCalc.ods | FPGA and ALPIDE radiation calculations]]&lt;br /&gt;
* [[:Media:Control Interface.pdf | pRU Control Interface]] [Deprecated, only in use on PTB. Replaced with IPBus on VCU118 + all other boards in the future.]&lt;br /&gt;
&lt;br /&gt;
==== pRU Registers and Bus System ====&lt;br /&gt;
[[File:Top level firmware.png|500px]][[File:Bus tree.png|500px]]&lt;br /&gt;
&lt;br /&gt;
The pRU bus system is connecting the various modules on the FPGA to a common master, the Microblaze Subsystem.&lt;br /&gt;
Each of the modules is associated with a given BASE-ADDRESS specified in the [[:Media:Control Interface.pdf | pRU Control Interface Document]].&lt;br /&gt;
Note that several instances do exist for certain modules. E.g. there are one alpide_data instance for each ALPIDE chip connected to the pRU.&lt;br /&gt;
To communicate with a specific instance one needs to add an offset of 0x1000 times the instance number to the module base address.&lt;br /&gt;
&lt;br /&gt;
E.g. if you want to communicate with the &lt;br /&gt;
&lt;br /&gt;
* 1st instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt;&lt;br /&gt;
&lt;br /&gt;
* 2nd instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt; + (0x1000 * (2-1))&lt;br /&gt;
&lt;br /&gt;
* 16th instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt; + (0x1000 * (16-1))&lt;br /&gt;
&lt;br /&gt;
===== Module Registers =====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Global_regs.pdf | global_regs]]&lt;br /&gt;
* [[:Media:Trigger_manager.pdf | trigger_manager]]&lt;br /&gt;
* [[:Media:Offload.pdf | offload]]&lt;br /&gt;
* [[:Media:Alpide_control.pdf | alpide_control]]&lt;br /&gt;
* [[:Media:Alpide_data.pdf | alpide_data]]&lt;br /&gt;
&lt;br /&gt;
==== PTB-specific Module Registers ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Power_control.pdf | power_control]]&lt;br /&gt;
* [[:Media:Ptb_regs.pdf | ptb_regs]]&lt;br /&gt;
&lt;br /&gt;
=== Transition Card (TC) ===&lt;br /&gt;
&lt;br /&gt;
*  [[Media:TC-v1.0_schematic.pdf | TC-v1.0 Schematic]]&lt;br /&gt;
&lt;br /&gt;
=== ALPIDE Chip ===&lt;br /&gt;
&lt;br /&gt;
* [[Media:Alpide manual ver3.pdf | ALPIDE Manual v0.3]]&lt;br /&gt;
&lt;br /&gt;
=== ALPIDE Bonding and Mounting ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Report_Feb_2019.pdf | 9-chip String Simulation - and proposed 9-chip string redesign - 2019 Feb ]]&lt;br /&gt;
&lt;br /&gt;
==== Chip Cable ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:2020_01_08.zip | 2020 January 8 ]]&lt;br /&gt;
* [[:Media:2019_05_16.zip | 2019 May 16 (ULTM)]]&lt;br /&gt;
&lt;br /&gt;
==== 9 Chip String ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:2019_11_05.zip | 2019 November 5 ]]&lt;br /&gt;
* Some of the aluminium traces on the flex cable broke by the tail of the cable (near the ZIF stiffener). [[:Media:Tail_modifications.png | Current design and possible modifications]] shows the current design and two possible modifications. It has been decided that new designs will use the design 1 modification and longer ZIF-stiffener (30 mm long).&lt;br /&gt;
&lt;br /&gt;
=== Production Test Box (PTB) ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:PTB-v1.0_schematic.pdf | PTB-v1.0 Schematic]]&lt;br /&gt;
* [[:Media:PTB-v1.0_samtec.zip | PTB-v1.0 FPGA Connections]]&lt;br /&gt;
* [[:Media:PTB-v1.0_yamaichi.zip | PTB-v1.0 Yamaichi Connections]]&lt;br /&gt;
&lt;br /&gt;
=== FPGA Mezzanine Card (FMC) ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:FMC-v1.0_schematic.pdf | FMC-v1.0 Schematic]]&lt;br /&gt;
&lt;br /&gt;
=== mTower ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:mTower_schematic.pdf | mTower Schematic]]&lt;br /&gt;
&lt;br /&gt;
=== Cooling Laboratory Setup ===&lt;br /&gt;
&lt;br /&gt;
LAUDA Ultracool UC 4 is used for water cooling in the laboratory now ([https://www.lauda.de/pim/datasheet/LAUDA_UC4_E6004411_en_20211220_135424.pdf data sheet] and [https://cdn.accentuate.io/6800432890013/1624628180288/DMI-0210-01_UC_2-4__EN_.pdf?v=0 manual]).&lt;/div&gt;</summary>
		<author><name>Xej010</name></author>
	</entry>
	<entry>
		<id>https://pct.wiki.uib.no/index.php?title=File:Tail_modifications.png&amp;diff=957</id>
		<title>File:Tail modifications.png</title>
		<link rel="alternate" type="text/html" href="https://pct.wiki.uib.no/index.php?title=File:Tail_modifications.png&amp;diff=957"/>
		<updated>2022-01-10T14:01:46Z</updated>

		<summary type="html">&lt;p&gt;Xej010: Xej010 uploaded a new version of File:Tail modifications.png&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;&lt;/div&gt;</summary>
		<author><name>Xej010</name></author>
	</entry>
	<entry>
		<id>https://pct.wiki.uib.no/index.php?title=File:Tail_modifications.png&amp;diff=956</id>
		<title>File:Tail modifications.png</title>
		<link rel="alternate" type="text/html" href="https://pct.wiki.uib.no/index.php?title=File:Tail_modifications.png&amp;diff=956"/>
		<updated>2022-01-10T13:56:31Z</updated>

		<summary type="html">&lt;p&gt;Xej010: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;&lt;/div&gt;</summary>
		<author><name>Xej010</name></author>
	</entry>
	<entry>
		<id>https://pct.wiki.uib.no/index.php?title=Hardware_Documentation_and_Howto%27s&amp;diff=955</id>
		<title>Hardware Documentation and Howto&#039;s</title>
		<link rel="alternate" type="text/html" href="https://pct.wiki.uib.no/index.php?title=Hardware_Documentation_and_Howto%27s&amp;diff=955"/>
		<updated>2022-01-10T13:54:51Z</updated>

		<summary type="html">&lt;p&gt;Xej010: /* 9 Chip String */&lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;[[Main Page]] -&amp;gt; [[Hardware Documentation and Howto&#039;s]]&lt;br /&gt;
&lt;br /&gt;
== Getting Started ==&lt;br /&gt;
&lt;br /&gt;
* [[Getting Started VCU118|VCU118]]&lt;br /&gt;
* [[Getting Started PTB|PTB]]&lt;br /&gt;
&lt;br /&gt;
== Documentation ==&lt;br /&gt;
&lt;br /&gt;
=== pRU ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Clock_network.png | pRU Clock Network]]&lt;br /&gt;
* [[:Media:PRU Address Map.pdf | pRU Address Map]]&lt;br /&gt;
* [[:Media:PRU Ethernet Configurations.pdf | DCS and Data Offload Ethernet Configurations]]&lt;br /&gt;
* [[:Media:PDTP.pdf | pCT Data Transfer Protocol]]&lt;br /&gt;
* [[:Media:Data format v0.2.pdf | pRU Data Format]]&lt;br /&gt;
* [[:Media:FpgaCalc.ods | FPGA and ALPIDE radiation calculations]]&lt;br /&gt;
* [[:Media:Control Interface.pdf | pRU Control Interface]] [Deprecated, only in use on PTB. Replaced with IPBus on VCU118 + all other boards in the future.]&lt;br /&gt;
&lt;br /&gt;
==== pRU Registers and Bus System ====&lt;br /&gt;
[[File:Top level firmware.png|500px]][[File:Bus tree.png|500px]]&lt;br /&gt;
&lt;br /&gt;
The pRU bus system is connecting the various modules on the FPGA to a common master, the Microblaze Subsystem.&lt;br /&gt;
Each of the modules is associated with a given BASE-ADDRESS specified in the [[:Media:Control Interface.pdf | pRU Control Interface Document]].&lt;br /&gt;
Note that several instances do exist for certain modules. E.g. there are one alpide_data instance for each ALPIDE chip connected to the pRU.&lt;br /&gt;
To communicate with a specific instance one needs to add an offset of 0x1000 times the instance number to the module base address.&lt;br /&gt;
&lt;br /&gt;
E.g. if you want to communicate with the &lt;br /&gt;
&lt;br /&gt;
* 1st instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt;&lt;br /&gt;
&lt;br /&gt;
* 2nd instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt; + (0x1000 * (2-1))&lt;br /&gt;
&lt;br /&gt;
* 16th instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt; + (0x1000 * (16-1))&lt;br /&gt;
&lt;br /&gt;
===== Module Registers =====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Global_regs.pdf | global_regs]]&lt;br /&gt;
* [[:Media:Trigger_manager.pdf | trigger_manager]]&lt;br /&gt;
* [[:Media:Offload.pdf | offload]]&lt;br /&gt;
* [[:Media:Alpide_control.pdf | alpide_control]]&lt;br /&gt;
* [[:Media:Alpide_data.pdf | alpide_data]]&lt;br /&gt;
&lt;br /&gt;
==== PTB-specific Module Registers ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Power_control.pdf | power_control]]&lt;br /&gt;
* [[:Media:Ptb_regs.pdf | ptb_regs]]&lt;br /&gt;
&lt;br /&gt;
=== Transition Card (TC) ===&lt;br /&gt;
&lt;br /&gt;
*  [[Media:TC-v1.0_schematic.pdf | TC-v1.0 Schematic]]&lt;br /&gt;
&lt;br /&gt;
=== ALPIDE Chip ===&lt;br /&gt;
&lt;br /&gt;
* [[Media:Alpide manual ver3.pdf | ALPIDE Manual v0.3]]&lt;br /&gt;
&lt;br /&gt;
=== ALPIDE Bonding and Mounting ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Report_Feb_2019.pdf | 9-chip String Simulation - and proposed 9-chip string redesign - 2019 Feb ]]&lt;br /&gt;
&lt;br /&gt;
==== Chip Cable ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:2020_01_08.zip | 2020 January 8 ]]&lt;br /&gt;
* [[:Media:2019_05_16.zip | 2019 May 16 (ULTM)]]&lt;br /&gt;
&lt;br /&gt;
==== 9 Chip String ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:2019_11_05.zip | 2019 November 5 ]]&lt;br /&gt;
* Some of the aluminium traces on the flex cable broke by the tail of the cable (near the ZIF stiffener). [[:Media:Tail_modifications.png &lt;br /&gt;
| Current design and possible modifications]] shows the current design and two possible modifications. It has been decided that new designs will use the design 1 modification and longer ZIF-stiffener (30 mm long).&lt;br /&gt;
&lt;br /&gt;
=== Production Test Box (PTB) ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:PTB-v1.0_schematic.pdf | PTB-v1.0 Schematic]]&lt;br /&gt;
* [[:Media:PTB-v1.0_samtec.zip | PTB-v1.0 FPGA Connections]]&lt;br /&gt;
* [[:Media:PTB-v1.0_yamaichi.zip | PTB-v1.0 Yamaichi Connections]]&lt;br /&gt;
&lt;br /&gt;
=== FPGA Mezzanine Card (FMC) ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:FMC-v1.0_schematic.pdf | FMC-v1.0 Schematic]]&lt;br /&gt;
&lt;br /&gt;
=== mTower ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:mTower_schematic.pdf | mTower Schematic]]&lt;br /&gt;
&lt;br /&gt;
=== Cooling Laboratory Setup ===&lt;br /&gt;
&lt;br /&gt;
LAUDA Ultracool UC 4 is used for water cooling in the laboratory now ([https://www.lauda.de/pim/datasheet/LAUDA_UC4_E6004411_en_20211220_135424.pdf data sheet] and [https://cdn.accentuate.io/6800432890013/1624628180288/DMI-0210-01_UC_2-4__EN_.pdf?v=0 manual]).&lt;/div&gt;</summary>
		<author><name>Xej010</name></author>
	</entry>
	<entry>
		<id>https://pct.wiki.uib.no/index.php?title=Hardware_Documentation_and_Howto%27s&amp;diff=954</id>
		<title>Hardware Documentation and Howto&#039;s</title>
		<link rel="alternate" type="text/html" href="https://pct.wiki.uib.no/index.php?title=Hardware_Documentation_and_Howto%27s&amp;diff=954"/>
		<updated>2022-01-10T13:33:13Z</updated>

		<summary type="html">&lt;p&gt;Xej010: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;[[Main Page]] -&amp;gt; [[Hardware Documentation and Howto&#039;s]]&lt;br /&gt;
&lt;br /&gt;
== Getting Started ==&lt;br /&gt;
&lt;br /&gt;
* [[Getting Started VCU118|VCU118]]&lt;br /&gt;
* [[Getting Started PTB|PTB]]&lt;br /&gt;
&lt;br /&gt;
== Documentation ==&lt;br /&gt;
&lt;br /&gt;
=== pRU ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Clock_network.png | pRU Clock Network]]&lt;br /&gt;
* [[:Media:PRU Address Map.pdf | pRU Address Map]]&lt;br /&gt;
* [[:Media:PRU Ethernet Configurations.pdf | DCS and Data Offload Ethernet Configurations]]&lt;br /&gt;
* [[:Media:PDTP.pdf | pCT Data Transfer Protocol]]&lt;br /&gt;
* [[:Media:Data format v0.2.pdf | pRU Data Format]]&lt;br /&gt;
* [[:Media:FpgaCalc.ods | FPGA and ALPIDE radiation calculations]]&lt;br /&gt;
* [[:Media:Control Interface.pdf | pRU Control Interface]] [Deprecated, only in use on PTB. Replaced with IPBus on VCU118 + all other boards in the future.]&lt;br /&gt;
&lt;br /&gt;
==== pRU Registers and Bus System ====&lt;br /&gt;
[[File:Top level firmware.png|500px]][[File:Bus tree.png|500px]]&lt;br /&gt;
&lt;br /&gt;
The pRU bus system is connecting the various modules on the FPGA to a common master, the Microblaze Subsystem.&lt;br /&gt;
Each of the modules is associated with a given BASE-ADDRESS specified in the [[:Media:Control Interface.pdf | pRU Control Interface Document]].&lt;br /&gt;
Note that several instances do exist for certain modules. E.g. there are one alpide_data instance for each ALPIDE chip connected to the pRU.&lt;br /&gt;
To communicate with a specific instance one needs to add an offset of 0x1000 times the instance number to the module base address.&lt;br /&gt;
&lt;br /&gt;
E.g. if you want to communicate with the &lt;br /&gt;
&lt;br /&gt;
* 1st instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt;&lt;br /&gt;
&lt;br /&gt;
* 2nd instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt; + (0x1000 * (2-1))&lt;br /&gt;
&lt;br /&gt;
* 16th instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt; + (0x1000 * (16-1))&lt;br /&gt;
&lt;br /&gt;
===== Module Registers =====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Global_regs.pdf | global_regs]]&lt;br /&gt;
* [[:Media:Trigger_manager.pdf | trigger_manager]]&lt;br /&gt;
* [[:Media:Offload.pdf | offload]]&lt;br /&gt;
* [[:Media:Alpide_control.pdf | alpide_control]]&lt;br /&gt;
* [[:Media:Alpide_data.pdf | alpide_data]]&lt;br /&gt;
&lt;br /&gt;
==== PTB-specific Module Registers ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Power_control.pdf | power_control]]&lt;br /&gt;
* [[:Media:Ptb_regs.pdf | ptb_regs]]&lt;br /&gt;
&lt;br /&gt;
=== Transition Card (TC) ===&lt;br /&gt;
&lt;br /&gt;
*  [[Media:TC-v1.0_schematic.pdf | TC-v1.0 Schematic]]&lt;br /&gt;
&lt;br /&gt;
=== ALPIDE Chip ===&lt;br /&gt;
&lt;br /&gt;
* [[Media:Alpide manual ver3.pdf | ALPIDE Manual v0.3]]&lt;br /&gt;
&lt;br /&gt;
=== ALPIDE Bonding and Mounting ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Report_Feb_2019.pdf | 9-chip String Simulation - and proposed 9-chip string redesign - 2019 Feb ]]&lt;br /&gt;
&lt;br /&gt;
==== Chip Cable ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:2020_01_08.zip | 2020 January 8 ]]&lt;br /&gt;
* [[:Media:2019_05_16.zip | 2019 May 16 (ULTM)]]&lt;br /&gt;
&lt;br /&gt;
==== 9 Chip String ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:2019_11_05.zip | 2019 November 5 ]]&lt;br /&gt;
&lt;br /&gt;
=== Production Test Box (PTB) ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:PTB-v1.0_schematic.pdf | PTB-v1.0 Schematic]]&lt;br /&gt;
* [[:Media:PTB-v1.0_samtec.zip | PTB-v1.0 FPGA Connections]]&lt;br /&gt;
* [[:Media:PTB-v1.0_yamaichi.zip | PTB-v1.0 Yamaichi Connections]]&lt;br /&gt;
&lt;br /&gt;
=== FPGA Mezzanine Card (FMC) ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:FMC-v1.0_schematic.pdf | FMC-v1.0 Schematic]]&lt;br /&gt;
&lt;br /&gt;
=== mTower ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:mTower_schematic.pdf | mTower Schematic]]&lt;br /&gt;
&lt;br /&gt;
=== Cooling Laboratory Setup ===&lt;br /&gt;
&lt;br /&gt;
LAUDA Ultracool UC 4 is used for water cooling in the laboratory now ([https://www.lauda.de/pim/datasheet/LAUDA_UC4_E6004411_en_20211220_135424.pdf data sheet] and [https://cdn.accentuate.io/6800432890013/1624628180288/DMI-0210-01_UC_2-4__EN_.pdf?v=0 manual]).&lt;/div&gt;</summary>
		<author><name>Xej010</name></author>
	</entry>
	<entry>
		<id>https://pct.wiki.uib.no/index.php?title=Hardware_Documentation_and_Howto%27s&amp;diff=655</id>
		<title>Hardware Documentation and Howto&#039;s</title>
		<link rel="alternate" type="text/html" href="https://pct.wiki.uib.no/index.php?title=Hardware_Documentation_and_Howto%27s&amp;diff=655"/>
		<updated>2020-01-14T10:29:55Z</updated>

		<summary type="html">&lt;p&gt;Xej010: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;== Getting Started ==&lt;br /&gt;
&lt;br /&gt;
* [[Getting Started VCU118|VCU118]]&lt;br /&gt;
* [[Getting Started PTB|PTB]]&lt;br /&gt;
&lt;br /&gt;
== Documentation ==&lt;br /&gt;
&lt;br /&gt;
=== pRU ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Control Interface.pdf | pRU Control Interface]]&lt;br /&gt;
* [[:Media:PRU Address Map.pdf | pRU Address Map]]&lt;br /&gt;
* [[:Media:PRU Ethernet Configurations.pdf | pRU Ethernet Configurations]]&lt;br /&gt;
* [[:Media:PDTP.pdf | pCT Data Transfer Protocol]]&lt;br /&gt;
* [[:Media:Data format v0.2.pdf | pRU Data Format]]&lt;br /&gt;
&lt;br /&gt;
==== pRU Registers and Bus System ====&lt;br /&gt;
[[File:Top level firmware.png|500px]][[File:Bus tree.png|500px]]&lt;br /&gt;
&lt;br /&gt;
The pRU bus system is connecting the various modules on the FPGA to a common master, the Microblaze Subsystem.&lt;br /&gt;
Each of the modules is associated with a given BASE-ADDRESS specified in the [[:Media:Control Interface.pdf | pRU Control Interface Document]].&lt;br /&gt;
Note that several instances do exist for certain modules. E.g. there are one alpide_data instance for each ALPIDE chip connected to the pRU.&lt;br /&gt;
To communicate with a specific instance one needs to add an offset of 0x1000 times the instance number to the module base address.&lt;br /&gt;
&lt;br /&gt;
E.g. if you want to communicate with the &lt;br /&gt;
&lt;br /&gt;
* 1st instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt;&lt;br /&gt;
&lt;br /&gt;
* 2nd instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt; + (0x1000 * (2-1))&lt;br /&gt;
&lt;br /&gt;
* 16th instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt; + (0x1000 * (16-1))&lt;br /&gt;
&lt;br /&gt;
===== Module Registers =====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Global_regs.pdf | global_regs]]&lt;br /&gt;
* [[:Media:Trigger_manager.pdf | trigger_manager]]&lt;br /&gt;
* [[:Media:Offload.pdf | offload]]&lt;br /&gt;
* [[:Media:Alpide_control.pdf | alpide_control]]&lt;br /&gt;
* [[:Media:Alpide_data.pdf | alpide_data]]&lt;br /&gt;
&lt;br /&gt;
==== PTB-specific Module Registers ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Power_control.pdf | power_control]]&lt;br /&gt;
* [[:Media:Ptb_regs.pdf | ptb_regs]]&lt;br /&gt;
&lt;br /&gt;
=== Transition Card (TC) ===&lt;br /&gt;
&lt;br /&gt;
*  [[Media:TC-v1.0_schematic.pdf | TC-v1.0_schematic]] &lt;br /&gt;
&lt;br /&gt;
=== ALPIDE Chip ===&lt;br /&gt;
&lt;br /&gt;
* [[Media:Alpide manual ver3.pdf | ALPIDE Manual v0.3]]&lt;br /&gt;
&lt;br /&gt;
=== ALPIDE Bonding and Mounting ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Report_Feb_2019.pdf | 9-chip String Simulation - and proposed 9-chip string redesign - 2019 Feb ]]&lt;br /&gt;
&lt;br /&gt;
==== Chip Cable ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:2020_01_08.zip | 2020 January 8 ]]&lt;br /&gt;
* [[:Media:2019_05_16.zip | 2019 May 16 (ULTM)]]&lt;br /&gt;
&lt;br /&gt;
==== 9 Chip String ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:2019_11_05.zip | 2019 November 5 ]]&lt;br /&gt;
&lt;br /&gt;
=== Production Test Box (PTB) ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:PTB-v1.0_schematic.pdf | PTB-v1.0 Schematic]]&lt;br /&gt;
* [[:Media:PTB-v1.0_samtec.zip | PTB-v1.0 FPGA Connections]]&lt;br /&gt;
* [[:Media:PTB-v1.0_yamaichi.zip | PTB-v1.0 Yamaichi Connections]]&lt;br /&gt;
&lt;br /&gt;
=== FPGA Mezzanine Card (FMC) ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:FMC-v1.0_schematic.pdf | FMC-v1.0 Schematic]]&lt;br /&gt;
&lt;br /&gt;
=== mTower ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:mTower_schematic.pdf | mTower Schematic]]&lt;/div&gt;</summary>
		<author><name>Xej010</name></author>
	</entry>
	<entry>
		<id>https://pct.wiki.uib.no/index.php?title=Hardware_Documentation_and_Howto%27s&amp;diff=654</id>
		<title>Hardware Documentation and Howto&#039;s</title>
		<link rel="alternate" type="text/html" href="https://pct.wiki.uib.no/index.php?title=Hardware_Documentation_and_Howto%27s&amp;diff=654"/>
		<updated>2020-01-14T10:27:48Z</updated>

		<summary type="html">&lt;p&gt;Xej010: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;== Getting Started ==&lt;br /&gt;
&lt;br /&gt;
* [[Getting Started VCU118|VCU118]]&lt;br /&gt;
* [[Getting Started PTB|PTB]]&lt;br /&gt;
&lt;br /&gt;
== Documentation ==&lt;br /&gt;
&lt;br /&gt;
=== pRU ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Control Interface.pdf | pRU Control Interface]]&lt;br /&gt;
* [[:Media:PRU Address Map.pdf | pRU Address Map]]&lt;br /&gt;
* [[:Media:PRU Ethernet Configurations.pdf | pRU Ethernet Configurations]]&lt;br /&gt;
* [[:Media:PDTP.pdf | pCT Data Transfer Protocol]]&lt;br /&gt;
* [[:Media:Data format v0.2.pdf | pRU Data Format]]&lt;br /&gt;
&lt;br /&gt;
==== pRU Registers and Bus System ====&lt;br /&gt;
[[File:Top level firmware.png|500px]][[File:Bus tree.png|500px]]&lt;br /&gt;
&lt;br /&gt;
The pRU bus system is connecting the various modules on the FPGA to a common master, the Microblaze Subsystem.&lt;br /&gt;
Each of the modules is associated with a given BASE-ADDRESS specified in the [[:Media:Control Interface.pdf | pRU Control Interface Document]].&lt;br /&gt;
Note that several instances do exist for certain modules. E.g. there are one alpide_data instance for each ALPIDE chip connected to the pRU.&lt;br /&gt;
To communicate with a specific instance one needs to add an offset of 0x1000 times the instance number to the module base address.&lt;br /&gt;
&lt;br /&gt;
E.g. if you want to communicate with the &lt;br /&gt;
&lt;br /&gt;
* 1st instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt;&lt;br /&gt;
&lt;br /&gt;
* 2nd instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt; + (0x1000 * (2-1))&lt;br /&gt;
&lt;br /&gt;
* 16th instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt; + (0x1000 * (16-1))&lt;br /&gt;
&lt;br /&gt;
===== Module Registers =====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Global_regs.pdf | global_regs]]&lt;br /&gt;
* [[:Media:Trigger_manager.pdf | trigger_manager]]&lt;br /&gt;
* [[:Media:Offload.pdf | offload]]&lt;br /&gt;
* [[:Media:Alpide_control.pdf | alpide_control]]&lt;br /&gt;
* [[:Media:Alpide_data.pdf | alpide_data]]&lt;br /&gt;
&lt;br /&gt;
==== PTB-specific Module Registers ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Power_control.pdf | power_control]]&lt;br /&gt;
* [[:Media:Ptb_regs.pdf | ptb_regs]]&lt;br /&gt;
&lt;br /&gt;
=== Transition Card (TC) ===&lt;br /&gt;
&lt;br /&gt;
*  [[:Media:TC-v1.0_schematic.pdf | TC-v1.0_schematic]] &lt;br /&gt;
&lt;br /&gt;
=== ALPIDE Chip ===&lt;br /&gt;
&lt;br /&gt;
* [[Media:Alpide manual ver3.pdf | ALPIDE Manual v0.3]]&lt;br /&gt;
&lt;br /&gt;
=== ALPIDE Bonding and Mounting ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Report_Feb_2019.pdf | 9-chip String Simulation - and proposed 9-chip string redesign - 2019 Feb ]]&lt;br /&gt;
&lt;br /&gt;
==== Chip Cable ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:2020_01_08.zip | 2020 January 8 ]]&lt;br /&gt;
* [[:Media:2019_05_16.zip | 2019 May 16 (ULTM)]]&lt;br /&gt;
&lt;br /&gt;
==== 9 Chip String ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:2019_11_05.zip | 2019 November 5 ]]&lt;br /&gt;
&lt;br /&gt;
=== Production Test Box (PTB) ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:PTB-v1.0_schematic.pdf | PTB-v1.0 Schematic]]&lt;br /&gt;
* [[:Media:PTB-v1.0_samtec.zip | PTB-v1.0 FPGA Connections]]&lt;br /&gt;
* [[:Media:PTB-v1.0_yamaichi.zip | PTB-v1.0 Yamaichi Connections]]&lt;br /&gt;
&lt;br /&gt;
=== FPGA Mezzanine Card (FMC) ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:FMC-v1.0_schematic.pdf | FMC-v1.0 Schematic]]&lt;br /&gt;
&lt;br /&gt;
=== mTower ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:mTower_schematic.pdf | mTower Schematic]]&lt;/div&gt;</summary>
		<author><name>Xej010</name></author>
	</entry>
	<entry>
		<id>https://pct.wiki.uib.no/index.php?title=File:TC-v1.0_schematic.pdf&amp;diff=653</id>
		<title>File:TC-v1.0 schematic.pdf</title>
		<link rel="alternate" type="text/html" href="https://pct.wiki.uib.no/index.php?title=File:TC-v1.0_schematic.pdf&amp;diff=653"/>
		<updated>2020-01-14T10:26:47Z</updated>

		<summary type="html">&lt;p&gt;Xej010: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;&lt;/div&gt;</summary>
		<author><name>Xej010</name></author>
	</entry>
	<entry>
		<id>https://pct.wiki.uib.no/index.php?title=Hardware_Documentation_and_Howto%27s&amp;diff=652</id>
		<title>Hardware Documentation and Howto&#039;s</title>
		<link rel="alternate" type="text/html" href="https://pct.wiki.uib.no/index.php?title=Hardware_Documentation_and_Howto%27s&amp;diff=652"/>
		<updated>2020-01-14T10:26:03Z</updated>

		<summary type="html">&lt;p&gt;Xej010: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;== Getting Started ==&lt;br /&gt;
&lt;br /&gt;
* [[Getting Started VCU118|VCU118]]&lt;br /&gt;
* [[Getting Started PTB|PTB]]&lt;br /&gt;
&lt;br /&gt;
== Documentation ==&lt;br /&gt;
&lt;br /&gt;
=== pRU ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Control Interface.pdf | pRU Control Interface]]&lt;br /&gt;
* [[:Media:PRU Address Map.pdf | pRU Address Map]]&lt;br /&gt;
* [[:Media:PRU Ethernet Configurations.pdf | pRU Ethernet Configurations]]&lt;br /&gt;
* [[:Media:PDTP.pdf | pCT Data Transfer Protocol]]&lt;br /&gt;
* [[:Media:Data format v0.2.pdf | pRU Data Format]]&lt;br /&gt;
&lt;br /&gt;
==== pRU Registers and Bus System ====&lt;br /&gt;
[[File:Top level firmware.png|500px]][[File:Bus tree.png|500px]]&lt;br /&gt;
&lt;br /&gt;
The pRU bus system is connecting the various modules on the FPGA to a common master, the Microblaze Subsystem.&lt;br /&gt;
Each of the modules is associated with a given BASE-ADDRESS specified in the [[:Media:Control Interface.pdf | pRU Control Interface Document]].&lt;br /&gt;
Note that several instances do exist for certain modules. E.g. there are one alpide_data instance for each ALPIDE chip connected to the pRU.&lt;br /&gt;
To communicate with a specific instance one needs to add an offset of 0x1000 times the instance number to the module base address.&lt;br /&gt;
&lt;br /&gt;
E.g. if you want to communicate with the &lt;br /&gt;
&lt;br /&gt;
* 1st instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt;&lt;br /&gt;
&lt;br /&gt;
* 2nd instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt; + (0x1000 * (2-1))&lt;br /&gt;
&lt;br /&gt;
* 16th instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt; + (0x1000 * (16-1))&lt;br /&gt;
&lt;br /&gt;
===== Module Registers =====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Global_regs.pdf | global_regs]]&lt;br /&gt;
* [[:Media:Trigger_manager.pdf | trigger_manager]]&lt;br /&gt;
* [[:Media:Offload.pdf | offload]]&lt;br /&gt;
* [[:Media:Alpide_control.pdf | alpide_control]]&lt;br /&gt;
* [[:Media:Alpide_data.pdf | alpide_data]]&lt;br /&gt;
&lt;br /&gt;
==== PTB-specific Module Registers ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Power_control.pdf | power_control]]&lt;br /&gt;
* [[:Media:Ptb_regs.pdf | ptb_regs]]&lt;br /&gt;
&lt;br /&gt;
=== Transition Card (TC) ===&lt;br /&gt;
&lt;br /&gt;
*  [[Media:TC-v1.0_schematic.pdf | TC-v1.0_schematic]]&lt;br /&gt;
&lt;br /&gt;
=== ALPIDE Chip ===&lt;br /&gt;
&lt;br /&gt;
* [[Media:Alpide manual ver3.pdf | ALPIDE Manual v0.3]]&lt;br /&gt;
&lt;br /&gt;
=== ALPIDE Bonding and Mounting ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Report_Feb_2019.pdf | 9-chip String Simulation - and proposed 9-chip string redesign - 2019 Feb ]]&lt;br /&gt;
&lt;br /&gt;
==== Chip Cable ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:2020_01_08.zip | 2020 January 8 ]]&lt;br /&gt;
* [[:Media:2019_05_16.zip | 2019 May 16 (ULTM)]]&lt;br /&gt;
&lt;br /&gt;
==== 9 Chip String ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:2019_11_05.zip | 2019 November 5 ]]&lt;br /&gt;
&lt;br /&gt;
=== Production Test Box (PTB) ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:PTB-v1.0_schematic.pdf | PTB-v1.0 Schematic]]&lt;br /&gt;
* [[:Media:PTB-v1.0_samtec.zip | PTB-v1.0 FPGA Connections]]&lt;br /&gt;
* [[:Media:PTB-v1.0_yamaichi.zip | PTB-v1.0 Yamaichi Connections]]&lt;br /&gt;
&lt;br /&gt;
=== FPGA Mezzanine Card (FMC) ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:FMC-v1.0_schematic.pdf | FMC-v1.0 Schematic]]&lt;br /&gt;
&lt;br /&gt;
=== mTower ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:mTower_schematic.pdf | mTower Schematic]]&lt;/div&gt;</summary>
		<author><name>Xej010</name></author>
	</entry>
	<entry>
		<id>https://pct.wiki.uib.no/index.php?title=Hardware_Documentation_and_Howto%27s&amp;diff=651</id>
		<title>Hardware Documentation and Howto&#039;s</title>
		<link rel="alternate" type="text/html" href="https://pct.wiki.uib.no/index.php?title=Hardware_Documentation_and_Howto%27s&amp;diff=651"/>
		<updated>2020-01-14T10:23:39Z</updated>

		<summary type="html">&lt;p&gt;Xej010: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;== Getting Started ==&lt;br /&gt;
&lt;br /&gt;
* [[Getting Started VCU118|VCU118]]&lt;br /&gt;
* [[Getting Started PTB|PTB]]&lt;br /&gt;
&lt;br /&gt;
== Documentation ==&lt;br /&gt;
&lt;br /&gt;
=== pRU ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Control Interface.pdf | pRU Control Interface]]&lt;br /&gt;
* [[:Media:PRU Address Map.pdf | pRU Address Map]]&lt;br /&gt;
* [[:Media:PRU Ethernet Configurations.pdf | pRU Ethernet Configurations]]&lt;br /&gt;
* [[:Media:PDTP.pdf | pCT Data Transfer Protocol]]&lt;br /&gt;
* [[:Media:Data format v0.2.pdf | pRU Data Format]]&lt;br /&gt;
&lt;br /&gt;
==== pRU Registers and Bus System ====&lt;br /&gt;
[[File:Top level firmware.png|500px]][[File:Bus tree.png|500px]]&lt;br /&gt;
&lt;br /&gt;
The pRU bus system is connecting the various modules on the FPGA to a common master, the Microblaze Subsystem.&lt;br /&gt;
Each of the modules is associated with a given BASE-ADDRESS specified in the [[:Media:Control Interface.pdf | pRU Control Interface Document]].&lt;br /&gt;
Note that several instances do exist for certain modules. E.g. there are one alpide_data instance for each ALPIDE chip connected to the pRU.&lt;br /&gt;
To communicate with a specific instance one needs to add an offset of 0x1000 times the instance number to the module base address.&lt;br /&gt;
&lt;br /&gt;
E.g. if you want to communicate with the &lt;br /&gt;
&lt;br /&gt;
* 1st instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt;&lt;br /&gt;
&lt;br /&gt;
* 2nd instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt; + (0x1000 * (2-1))&lt;br /&gt;
&lt;br /&gt;
* 16th instance: &amp;lt;ALPIDE_DATA_BASEADDR&amp;gt; + (0x1000 * (16-1))&lt;br /&gt;
&lt;br /&gt;
===== Module Registers =====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Global_regs.pdf | global_regs]]&lt;br /&gt;
* [[:Media:Trigger_manager.pdf | trigger_manager]]&lt;br /&gt;
* [[:Media:Offload.pdf | offload]]&lt;br /&gt;
* [[:Media:Alpide_control.pdf | alpide_control]]&lt;br /&gt;
* [[:Media:Alpide_data.pdf | alpide_data]]&lt;br /&gt;
&lt;br /&gt;
==== PTB-specific Module Registers ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Power_control.pdf | power_control]]&lt;br /&gt;
* [[:Media:Ptb_regs.pdf | ptb_regs]]&lt;br /&gt;
&lt;br /&gt;
=== Transition Card (TC) ===&lt;br /&gt;
&lt;br /&gt;
*  [[Media:TC-v1.0_schematic.pdf | Transition Card Schematics v1.0]]&lt;br /&gt;
&lt;br /&gt;
=== ALPIDE Chip ===&lt;br /&gt;
&lt;br /&gt;
* [[Media:Alpide manual ver3.pdf | ALPIDE Manual v0.3]]&lt;br /&gt;
&lt;br /&gt;
=== ALPIDE Bonding and Mounting ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:Report_Feb_2019.pdf | 9-chip String Simulation - and proposed 9-chip string redesign - 2019 Feb ]]&lt;br /&gt;
&lt;br /&gt;
==== Chip Cable ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:2020_01_08.zip | 2020 January 8 ]]&lt;br /&gt;
* [[:Media:2019_05_16.zip | 2019 May 16 (ULTM)]]&lt;br /&gt;
&lt;br /&gt;
==== 9 Chip String ====&lt;br /&gt;
&lt;br /&gt;
* [[:Media:2019_11_05.zip | 2019 November 5 ]]&lt;br /&gt;
&lt;br /&gt;
=== Production Test Box (PTB) ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:PTB-v1.0_schematic.pdf | PTB-v1.0 Schematic]]&lt;br /&gt;
* [[:Media:PTB-v1.0_samtec.zip | PTB-v1.0 FPGA Connections]]&lt;br /&gt;
* [[:Media:PTB-v1.0_yamaichi.zip | PTB-v1.0 Yamaichi Connections]]&lt;br /&gt;
&lt;br /&gt;
=== FPGA Mezzanine Card (FMC) ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:FMC-v1.0_schematic.pdf | FMC-v1.0 Schematic]]&lt;br /&gt;
&lt;br /&gt;
=== mTower ===&lt;br /&gt;
&lt;br /&gt;
* [[:Media:mTower_schematic.pdf | mTower Schematic]]&lt;/div&gt;</summary>
		<author><name>Xej010</name></author>
	</entry>
	<entry>
		<id>https://pct.wiki.uib.no/index.php?title=File:TC_V1.0_schematic.pdf&amp;diff=650</id>
		<title>File:TC V1.0 schematic.pdf</title>
		<link rel="alternate" type="text/html" href="https://pct.wiki.uib.no/index.php?title=File:TC_V1.0_schematic.pdf&amp;diff=650"/>
		<updated>2020-01-12T14:07:55Z</updated>

		<summary type="html">&lt;p&gt;Xej010: &lt;/p&gt;
&lt;hr /&gt;
&lt;div&gt;&lt;/div&gt;</summary>
		<author><name>Xej010</name></author>
	</entry>
</feed>