Hardware Documentation and Howto's: Difference between revisions
From pCT
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* [[:Media:Global_regs.pdf | global_regs]] | * [[:Media:Global_regs.pdf | global_regs]] | ||
* [[:Media:Trigger_manager.pdf | trigger_manager]] | * [[:Media:Trigger_manager.pdf | trigger_manager]] | ||
* offload | * [[:Media:Offload.pdf | offload]] | ||
* [[:Media:Alpide_control.pdf | alpide_control]] | * [[:Media:Alpide_control.pdf | alpide_control]] | ||
* [[:Media:Alpide_data.pdf | alpide_data]] | * [[:Media:Alpide_data.pdf | alpide_data]] | ||
Revision as of 14:26, 15 September 2019
Getting Started
Documentation
pRU
pRU Registers and Bus System
The pRU bus system is connecting the various modules on the FPGA to a common master, the Microblaze Subsystem. Each of the modules is associated with a given BASE-ADDRESS specified in the pRU Control Interface Document. Note that several instances do exist for certain modules. E.g. there are one alpide_data instance for each ALPIDE chip connected to the pRU. To communicate with a specific instance one needs to add an offset of 0x1000 times the instance number to the module base address.
E.g. if you want to communicate with the
- 1st instance: <ALPIDE_DATA_BASEADDR>
- 2nd instance: <ALPIDE_DATA_BASEADDR> + (0x1000 * 2-1)
- 16th instance: <ALPIDE_DATA_BASEADDR> + (0x1000 * 16-1)
