Hardware Documentation and Howto's

Main Page -> Hardware Documentation and Howto's

Getting Started

• VCU118
• PTB

Documentation

pRU

• pRU Clock Network
• pRU Address Map
• DCS and Data Offload Ethernet Configurations
• pCT Data Transfer Protocol
• pRU Data Format
• FPGA and ALPIDE radiation calculations
• pRU Control Interface [Deprecated, only in use on PTB. Replaced with IPBus on VCU118 + all other boards in the future.]

pRU Registers and Bus System

The pRU bus system is connecting the various modules on the FPGA to a common master, the Microblaze Subsystem. Each of the modules is associated with a given BASE-ADDRESS specified in the pRU Control Interface Document. Note that several instances do exist for certain modules. E.g. there are one alpide_data instance for each ALPIDE chip connected to the pRU. To communicate with a specific instance one needs to add an offset of 0x1000 times the instance number to the module base address.

E.g. if you want to communicate with the

• 1st instance: <ALPIDE_DATA_BASEADDR>

• 2nd instance: <ALPIDE_DATA_BASEADDR> + (0x1000 * (2-1))

• 16th instance: <ALPIDE_DATA_BASEADDR> + (0x1000 * (16-1))

Module Registers

• global_regs
• trigger_manager
• offload
• alpide_control
• alpide_data

PTB-specific Module Registers

• power_control
• ptb_regs

Transition Card (TC)

• TC-v1.0 Schematic

ALPIDE Chip

• ALPIDE Manual v0.3

ALPIDE Bonding and Mounting

• 9-chip String Simulation - and proposed 9-chip string redesign - 2019 Feb

Chip Cable

• 2020 January 8
• 2019 May 16 (ULTM)

9 Chip String

• 2019 November 5

Production Test Box (PTB)

• PTB-v1.0 Schematic
• PTB-v1.0 FPGA Connections
• PTB-v1.0 Yamaichi Connections

FPGA Mezzanine Card (FMC)

• FMC-v1.0 Schematic

mTower

• mTower Schematic

Cooling Laboratory Setup

LAUDA Ultracool UC 4 is used for water cooling in the laboratory now (data sheet and manual).